util: disassembler register/address mapping fix
For def/use pruning, the linear address mapping of the x86 sub-registers (e.g., AX represents the lower 16 bits of EAX) must overlap. If it doesn't, e.g., AX and EAX are considered separate registers by def/use pruning, resulting in a failure to correlate an EAX def with a subsequent AX use. The only user of this mapping up to now, RegisterImporter, forced all register widths to 8 bits, thereby fortunately canceling out this problem. Nevertheless it makes no sense to continue encoding a constant width in these virtual addresses. Existing trace, fspgroup, fsppilot and result tables may be converted to the new encoding by using this query: UPDATE <tablename> SET data_address = ((data_address >> 4) & ~0xf) | data_address & 0xf; Change-Id: I7a942b78c34f6140803a86af639eeedef3550f34
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@ -13,6 +13,12 @@ namespace fail {
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*/
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class LLVMtoFailTranslator {
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public:
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/**
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* Maps registers to/from linear addresses usable for def/use-pruning
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* purposes and storage in the database. Takes care that the linear
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* addresses of x86 subregisters (e.g., AX represents the lower 16 bits of
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* EAX) overlap with their siblings.
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*/
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struct reginfo_t {
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int id;
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regwidth_t width;
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@ -20,18 +26,17 @@ public:
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byte_t offset;
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int toDataAddress() const {
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// .. 5 4 | 7 6 5 4 | 3 2 1 0
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// <reg> | <width> | <offset>
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return (id << 8) | ((width/8) << 4) | (offset / 8);
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// .. 5 4 | 3 2 1 0
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// <reg> | <offset>
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return (id << 4) | (offset / 8);
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}
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// does not recreate width or mask
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static reginfo_t fromDataAddress(int addr) {
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int id = addr >> 8;
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regwidth_t width = ((addr >> 4) & 0xf) * 8;
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byte_t offset = (addr & 0xf) * 8;
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return reginfo_t(id, width, offset);
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int id = addr >> 4;
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byte_t offset = (addr & 0xf) * 8;
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return reginfo_t(id, 0, offset);
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}
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reginfo_t(int id=-1, regwidth_t width = 32, byte_t offs = 0)
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: id(id), width(width), mask((regwidth_t)((((long long)1 << width) - 1) << offs)), offset(offs) {};
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};
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