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gem5: adapt to Register iface change

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This change adapts the gem5 backend to the Register class interface change
in commit 52723a8.  The necessary modifications suggested adding the "misc"
registers from gem5, too.

Change-Id: I32561c3fc905b9cd396e32ce80c791c01d5682fb
This commit is contained in:
Horst Schirmeier
2013-08-29 19:33:55 +02:00
parent 4115de91aa
commit 0e595b38a3
4 changed files with 217 additions and 27 deletions
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4
src/core/sal/gem5/Gem5ArmCPU.cc
View File

@ -6,12 +6,12 @@ namespace fail {
regdata_t Gem5ArmCPU::getRegisterContent(const Register* reg) const
{
return GetRegisterContent(m_System, m_Id, reg->getType(), reg->getIndex());
return GetRegisterContent(m_System, m_Id, reg->getId());
}
void Gem5ArmCPU::setRegisterContent(const Register* reg, regdata_t value)
{
SetRegisterContent(m_System, m_Id, reg->getType(), reg->getIndex(), value);
SetRegisterContent(m_System, m_Id, reg->getId(), value);
}
} // end-of-namespace: fail

35
src/core/sal/gem5/Gem5Wrapper.cc
View File

@ -8,30 +8,31 @@
namespace fail {
// Register-/Memory-related:
regdata_t GetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx)
regdata_t GetRegisterContent(System* sys, unsigned int id, size_t idx)
{
switch (type) {
case RT_GP: // pass on...
case RT_FP: return sys->getThreadContext(id)->readIntReg(idx);
case RT_ST: return sys->getThreadContext(id)->readMiscReg(idx);
case RT_IP: return sys->getThreadContext(id)->pcState().pc();
// necessary because gem5 register IDs are not unique
if (idx < RI_INTREGS_MAX) {
switch (idx) {
case RI_IP: return sys->getThreadContext(id)->pcState().pc();
default: return sys->getThreadContext(id)->readIntReg(idx);
}
} else {
return sys->getThreadContext(id)->readMiscReg(idx - RI_INTREGS_MAX);
}
// This shouldn't be reached if a valid register is passed
assert(false && "FATAL ERROR: invalid register type (should never be reached)!");
return 0;
}
void SetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx,
regdata_t value)
void SetRegisterContent(System* sys, unsigned int id, size_t idx, regdata_t value)
{
switch (type) {
case RT_GP: // pass on...
case RT_FP: sys->getThreadContext(id)->setIntReg(idx, value); return;
case RT_ST: sys->getThreadContext(id)->setMiscReg(idx, value); return;
case RT_IP: sys->getThreadContext(id)->pcState().pc(static_cast<Addr>(value)); return;
// necessary because gem5 register IDs are not unique
if (idx < RI_INTREGS_MAX) {
switch (idx) {
case RI_IP: sys->getThreadContext(id)->pcState().pc(static_cast<Addr>(value)); break;
default: sys->getThreadContext(id)->setIntReg(idx, value);
}
} else {
sys->getThreadContext(id)->setMiscReg(idx - RI_INTREGS_MAX, value);
}
// This shouldn't be reached if a valid register is passed
assert(false && "FATAL ERROR: Invalid register type (should never be reached)!");
}
void ReadMemory(System* sys, guest_address_t addr, size_t cnt, void *dest)

5
src/core/sal/gem5/Gem5Wrapper.hpp
View File

@ -10,9 +10,8 @@ class System;
namespace fail {
// Register-/Memory-related:
regdata_t GetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx);
void SetRegisterContent(System* sys, unsigned int id, RegisterType type, size_t idx,
regdata_t value);
regdata_t GetRegisterContent(System* sys, unsigned int id, size_t idx);
void SetRegisterContent(System* sys, unsigned int id, size_t idx, regdata_t value);
void WriteMemory(System* sys, guest_address_t addr, size_t cnt, void const *src);
void ReadMemory(System* sys, guest_address_t addr, size_t cnt, void *dest);
size_t GetPoolSize(System* sys);