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gem5 build system improved

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Encapsulated gem5-specific code into wrapper functions to separate the
build process (Fail: CMake, gem5: scons). Added some gem5-related FIXMEs.

Another CMake related FIXME added. +some cosmetics.

Change-Id: Id84b480127b1f13aed6a0ee97f3583f410d531c5
This commit is contained in:
Adrian Böckenkamp
2013-04-04 17:30:10 +02:00
parent 84559fe467
commit 08febe5819
14 changed files with 252 additions and 123 deletions
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34
src/core/sal/gem5/Gem5ArmCPU.cc
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@ -1,43 +1,17 @@
#include "Gem5ArmCPU.hpp"
#include "Gem5Wrapper.hpp"
namespace fail {
regdata_t Gem5ArmCPU::getRegisterContent(Register* reg) const
{
switch (reg->getType()) {
case RT_GP:
if (reg->getIndex() == 15) {
return m_System->getThreadContext(m_Id)->pcState().pc();
}
return m_System->getThreadContext(m_Id)->readIntReg(reg->getIndex());
case RT_FP:
return m_System->getThreadContext(m_Id)->readFloatReg(reg->getIndex());
case RT_ST:
return m_System->getThreadContext(m_Id)->readMiscReg(reg->getIndex());
case RT_IP:
return m_System->getThreadContext(m_Id)->pcState().pc();
}
// This shouldn't be reached if a valid register is passed
// TODO: assertion?
return 0;
return GetRegisterContent(m_System, m_Id, reg->getType(), reg->getIndex());
}
void Gem5ArmCPU::setRegisterContent(Register* reg, regdata_t value)
{
switch (reg->getType()) {
case RT_GP:
m_System->getThreadContext(m_Id)->setIntReg(reg->getIndex(), value);
break;
case RT_FP:
m_System->getThreadContext(m_Id)->setFloatReg(reg->getIndex(), value);
break;
case RT_ST:
return m_System->getThreadContext(m_Id)->setMiscReg(reg->getIndex(), value);
case RT_IP:
return setRegisterContent(getRegister(RI_IP), value);
}
// TODO: assertion?
SetRegisterContent(m_System, m_Id, reg->getType(), reg->getIndex(), value);
}
} // end-of-namespace: fail