
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000020                       # Number of seconds simulated
sim_ticks                                    19775000                       # Number of ticks simulated
final_tick                                   19775000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                  79967                       # Simulator instruction rate (inst/s)
host_op_rate                                    79947                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              271245925                       # Simulator tick rate (ticks/s)
host_mem_usage                                 215348                       # Number of bytes of host memory used
host_seconds                                     0.07                       # Real time elapsed on the host
sim_insts                                        5827                       # Number of instructions simulated
sim_ops                                          5827                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
system.physmem.bytes_read::total                29120                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        20288                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           20288                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst                317                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                   455                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst           1025941846                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data            446624526                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total              1472566372                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst      1025941846                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total         1025941846                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst          1025941846                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data           446624526                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total             1472566372                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                    8                       # Number of system calls
system.cpu.numCycles                            39551                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.branch_predictor.lookups              1152                       # Number of BP lookups
system.cpu.branch_predictor.condPredicted          851                       # Number of conditional branches predicted
system.cpu.branch_predictor.condIncorrect          605                       # Number of conditional branches incorrect
system.cpu.branch_predictor.BTBLookups            867                       # Number of BTB lookups
system.cpu.branch_predictor.BTBHits               309                       # Number of BTB hits
system.cpu.branch_predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect           32                       # Number of incorrect RAS predictions.
system.cpu.branch_predictor.BTBHitPct       35.640138                       # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken          402                       # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken          750                       # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads         5104                       # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites         3408                       # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses         8512                       # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards           1330                       # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens                       2238                       # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect          262                       # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect          334                       # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted            596                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted               320                       # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct     65.065502                       # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions             3155                       # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
system.cpu.contextSwitches                          1                       # Number of context switches
system.cpu.threadCycles                          9142                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled                             404                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                           34183                       # Number of cycles cpu's stages were not processed
system.cpu.runCycles                             5368                       # Number of cycles cpu stages are processed.
system.cpu.activity                         13.572350                       # Percentage of cycles cpu is active
system.cpu.comLoads                              1164                       # Number of Load instructions committed
system.cpu.comStores                              925                       # Number of Store instructions committed
system.cpu.comBranches                            916                       # Number of Branches instructions committed
system.cpu.comNops                                657                       # Number of Nop instructions committed
system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
system.cpu.comInts                               2155                       # Number of Integer instructions committed
system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
system.cpu.committedInsts                        5827                       # Number of Instructions committed (Per-Thread)
system.cpu.committedOps                          5827                       # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total                  5827                       # Number of Instructions committed (Total)
system.cpu.cpi                               6.787541                       # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
system.cpu.cpi_total                         6.787541                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.147329                       # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
system.cpu.ipc_total                         0.147329                       # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles                    35911                       # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles                      3640                       # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization                9.203307                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles                    36722                       # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles                      2829                       # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization                7.152790                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles                    36760                       # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles                      2791                       # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization                7.056712                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles                    38308                       # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles                      1243                       # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization                3.142778                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles                    36647                       # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles                      2904                       # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization                7.342419                       # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements                     13                       # number of replacements
system.cpu.icache.tagsinuse                148.175887                       # Cycle average of tags in use
system.cpu.icache.total_refs                      411                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    319                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                   1.288401                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     148.175887                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.072352                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.072352                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst          411                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total             411                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst           411                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total              411                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst          411                       # number of overall hits
system.cpu.icache.overall_hits::total             411                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          343                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           343                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          343                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            343                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          343                       # number of overall misses
system.cpu.icache.overall_misses::total           343                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     19128500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     19128500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     19128500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     19128500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     19128500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     19128500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst          754                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total          754                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst          754                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total          754                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst          754                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total          754                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.454907                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.454907                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.454907                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.454907                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.454907                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.454907                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55768.221574                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 55768.221574                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 55768.221574                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               1                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets        29000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst           24                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total           24                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst           24                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total           24                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst           24                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total           24                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          319                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          319                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          319                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16951500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     16951500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16951500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     16951500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16951500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     16951500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.423077                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.423077                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.423077                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.423077                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53139.498433                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 53139.498433                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53139.498433                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                      0                       # number of replacements
system.cpu.dcache.tagsinuse                 89.746602                       # Cycle average of tags in use
system.cpu.dcache.total_refs                     1838                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  13.318841                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data      89.746602                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.021911                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.021911                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data         1075                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total            1075                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data          763                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total            763                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data          1838                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total             1838                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data         1838                       # number of overall hits
system.cpu.dcache.overall_hits::total            1838                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data           89                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total            89                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data          162                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total          162                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data          251                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total            251                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data          251                       # number of overall misses
system.cpu.dcache.overall_misses::total           251                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data      5072500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total      5072500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data      8910500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total      8910500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data     13983000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total     13983000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data     13983000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total     13983000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data         2089                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total         2089                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076460                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.076460                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.175135                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.175135                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.120153                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.120153                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.120153                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.120153                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 56994.382022                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 55003.086420                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 55709.163347                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 55709.163347                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets      1153500                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets              23                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data          111                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total          111                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total          113                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4702500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total      4702500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2745500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total      2745500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7448000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total      7448000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7448000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total      7448000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074742                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.066060                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.066060                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54051.724138                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53833.333333                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 53971.014493                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53971.014493                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                     0                       # number of replacements
system.cpu.l2cache.tagsinuse               205.517886                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                   404                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  0.004950                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::cpu.inst    149.817885                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data     55.700002                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::cpu.inst     0.004572                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.001700                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.006272                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          317                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total          404                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          317                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total           455                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16585000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4585000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total     21170000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2682000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total      2682000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     16585000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data      7267000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total     23852000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     16585000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data      7267000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total     23852000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          319                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total          457                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          319                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total          457                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993730                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.995074                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993730                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.995624                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 52400.990099                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52588.235294                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52421.978022                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52421.978022                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          317                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total          404                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          317                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total          455                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          317                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total          455                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12717500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3529500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16247000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2058000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2058000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12717500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5587500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total     18305000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12717500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5587500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total     18305000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.995074                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.995624                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.995624                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40215.346535                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40352.941176                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40230.769231                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40230.769231                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
