
---------- Begin Simulation Statistics ----------
sim_seconds                                  0.000263                       # Number of seconds simulated
sim_ticks                                   263488655                       # Number of ticks simulated
final_tick                                  263488655                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_tick_rate                                1558675                       # Simulator tick rate (ticks/s)
host_mem_usage                                 343952                       # Number of bytes of host memory used
host_seconds                                   169.05                       # Real time elapsed on the host
system.physmem.bytes_read::cpu0                504730                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1                513456                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu2                503221                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu3                509883                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu4                511138                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu5                501110                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu6                514161                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu7                499881                       # Number of bytes read from this memory
system.physmem.bytes_read::total              4057580                       # Number of bytes read from this memory
system.physmem.bytes_written::writebacks      2601216                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0               5392                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1               5426                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu2               5325                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu3               5406                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu4               5472                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu5               5362                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu6               5419                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu7               5298                       # Number of bytes written to this memory
system.physmem.bytes_written::total           2644316                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0                  17740                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1                  17646                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2                  17743                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3                  17727                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu4                  17848                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu5                  17774                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu6                  17658                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu7                  17742                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                141878                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           40644                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0                  5392                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1                  5426                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2                  5325                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu3                  5406                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu4                  5472                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu5                  5362                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu6                  5419                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu7                  5298                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                83744                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0               1915566346                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1               1948683521                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2               1909839344                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu3               1935123165                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu4               1939886178                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu5               1901827614                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu6               1951359158                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu7               1897163276                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total             15399448602                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks        9872212525                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0                20463879                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1                20592917                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2                20209599                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu3                20517012                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu4                20767498                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu5                20350022                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu6                20566350                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu7                20107128                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total            10035786930                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks        9872212525                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0              1936030225                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1              1969276438                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2              1930048943                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu3              1955640177                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu4              1960653676                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu5              1922177636                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu6              1971925509                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu7              1917270404                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total            25435235532                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                         76856                       # number of replacements
system.l2c.tagsinuse                       657.714518                       # Cycle average of tags in use
system.l2c.total_refs                          139150                       # Total number of references to valid blocks.
system.l2c.sampled_refs                         77525                       # Sample count of references to valid blocks.
system.l2c.avg_refs                          1.794905                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks          468.019905                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu0                 24.077198                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu1                 23.899612                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu2                 23.566419                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu3                 24.461210                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu4                 24.025606                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu5                 23.167376                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu6                 23.494200                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu7                 23.002994                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.457051                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu0                 0.023513                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu1                 0.023339                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu2                 0.023014                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu3                 0.023888                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu4                 0.023463                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu5                 0.022624                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu6                 0.022944                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu7                 0.022464                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.642299                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu0                   10466                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1                   10370                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2                   10579                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu3                   10469                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu4                   10390                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu5                   10384                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu6                   10590                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu7                   10463                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                  83711                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks           94038                       # number of Writeback hits
system.l2c.Writeback_hits::total                94038                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0                  457                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1                  419                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2                  446                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu3                  463                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu4                  430                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu5                  463                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu6                  415                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu7                  411                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                3504                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu0                  2829                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1                  2819                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2                  2901                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu3                  2765                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu4                  2827                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu5                  2929                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu6                  2882                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu7                  2913                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                22865                       # number of ReadExReq hits
system.l2c.demand_hits::cpu0                    13295                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1                    13189                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu2                    13480                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu3                    13234                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu4                    13217                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu5                    13313                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu6                    13472                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu7                    13376                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  106576                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0                   13295                       # number of overall hits
system.l2c.overall_hits::cpu1                   13189                       # number of overall hits
system.l2c.overall_hits::cpu2                   13480                       # number of overall hits
system.l2c.overall_hits::cpu3                   13234                       # number of overall hits
system.l2c.overall_hits::cpu4                   13217                       # number of overall hits
system.l2c.overall_hits::cpu5                   13313                       # number of overall hits
system.l2c.overall_hits::cpu6                   13472                       # number of overall hits
system.l2c.overall_hits::cpu7                   13376                       # number of overall hits
system.l2c.overall_hits::total                 106576                       # number of overall hits
system.l2c.ReadReq_misses::cpu0                  5163                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1                  5186                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2                  5173                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu3                  5223                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu4                  5193                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu5                  5114                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu6                  5145                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu7                  4996                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                41193                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0               1644                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1               1598                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2               1617                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu3               1610                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu4               1586                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu5               1626                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu6               1624                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu7               1582                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             12887                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0                5539                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1                5808                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2                5466                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu3                5538                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu4                5599                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu5                5507                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu6                5800                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu7                5643                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total              44900                       # number of ReadExReq misses
system.l2c.demand_misses::cpu0                  10702                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1                  10994                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu2                  10639                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu3                  10761                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu4                  10792                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu5                  10621                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu6                  10945                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu7                  10639                       # number of demand (read+write) misses
system.l2c.demand_misses::total                 86093                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0                 10702                       # number of overall misses
system.l2c.overall_misses::cpu1                 10994                       # number of overall misses
system.l2c.overall_misses::cpu2                 10639                       # number of overall misses
system.l2c.overall_misses::cpu3                 10761                       # number of overall misses
system.l2c.overall_misses::cpu4                 10792                       # number of overall misses
system.l2c.overall_misses::cpu5                 10621                       # number of overall misses
system.l2c.overall_misses::cpu6                 10945                       # number of overall misses
system.l2c.overall_misses::cpu7                 10639                       # number of overall misses
system.l2c.overall_misses::total                86093                       # number of overall misses
system.l2c.ReadReq_miss_latency::cpu0       256196985                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1       257287128                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2       256567876                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu3       259144977                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu4       257572428                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu5       253877351                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu6       255352806                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu7       247792064                       # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total     2043791615                       # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu0     32636387                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1     33737386                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2     32855972                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu3     32255171                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu4     31405634                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu5     33663875                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu6     32311068                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu7     32543105                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    261408598                       # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0     275716926                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1     289198618                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2     271873258                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu3     276122659                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu4     279168031                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu5     274243794                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu6     289241297                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu7     281223785                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total   2236788368                       # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu0        531913911                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1        546485746                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2        528441134                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu3        535267636                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu4        536740459                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu5        528121145                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu6        544594103                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu7        529015849                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total      4280579983                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0       531913911                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1       546485746                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2       528441134                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu3       535267636                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu4       536740459                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu5       528121145                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu6       544594103                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu7       529015849                       # number of overall miss cycles
system.l2c.overall_miss_latency::total     4280579983                       # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0               15629                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1               15556                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2               15752                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu3               15692                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu4               15583                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu5               15498                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu6               15735                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu7               15459                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total             124904                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks        94038                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total            94038                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0             2101                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1             2017                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2             2063                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu3             2073                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu4             2016                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu5             2089                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu6             2039                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu7             1993                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           16391                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0              8368                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1              8627                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2              8367                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu3              8303                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu4              8426                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu5              8436                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu6              8682                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu7              8556                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total            67765                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0                23997                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1                24183                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2                24119                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu3                23995                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu4                24009                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu5                23934                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu6                24417                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu7                24015                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              192669                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0               23997                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1               24183                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2               24119                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3               23995                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu4               24009                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu5               23934                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu6               24417                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu7               24015                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             192669                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0           0.330347                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1           0.333376                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2           0.328403                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu3           0.332845                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu4           0.333248                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu5           0.329978                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu6           0.326978                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu7           0.323177                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.329797                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0        0.782485                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1        0.792266                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2        0.783810                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu3        0.776652                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu4        0.786706                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu5        0.778363                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu6        0.796469                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu7        0.793778                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.786224                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0         0.661926                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1         0.673235                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2         0.653281                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu3         0.666988                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu4         0.664491                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu5         0.652798                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu6         0.668049                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu7         0.659537                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.662584                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0            0.445972                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1            0.454617                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2            0.441105                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu3            0.448468                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu4            0.449498                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu5            0.443762                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu6            0.448253                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu7            0.443015                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.446844                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0           0.445972                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1           0.454617                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2           0.441105                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu3           0.448468                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu4           0.449498                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu5           0.443762                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu6           0.448253                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu7           0.443015                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.446844                       # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu3 49616.116600                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273                       # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 49615.022334                       # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu3 20034.267702                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 20284.674323                       # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu3 49859.635067                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 49817.112873                       # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu0 49702.290320                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1 49707.635619                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2 49670.188364                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu3 49741.440015                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu4 49735.031412                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu5 49724.239243                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu6 49757.341526                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu7 49724.208008                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 49720.418420                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0 49702.290320                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1 49707.635619                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2 49670.188364                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu3 49741.440015                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu4 49735.031412                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu5 49724.239243                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu6 49757.341526                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu7 49724.208008                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 49720.418420                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             97509                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks               40644                       # number of writebacks
system.l2c.writebacks::total                    40644                       # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu0                118                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu1                121                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2                142                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu3                119                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu4                123                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu5                114                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu6                110                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu7                114                       # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total               961                       # number of ReadReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu0               7                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu1               8                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu2               5                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu3               7                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu4               6                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu5               5                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu6               5                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::cpu7               6                       # number of UpgradeReq MSHR hits
system.l2c.UpgradeReq_mshr_hits::total             49                       # number of UpgradeReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu0               68                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu1               72                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu2               73                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu3               47                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu4               55                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu5               72                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu6               58                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::cpu7               62                       # number of ReadExReq MSHR hits
system.l2c.ReadExReq_mshr_hits::total             507                       # number of ReadExReq MSHR hits
system.l2c.demand_mshr_hits::cpu0                 186                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1                 193                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2                 215                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3                 166                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu4                 178                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu5                 186                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu6                 168                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu7                 176                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total               1468                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0                186                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1                193                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2                215                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3                166                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu4                178                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu5                186                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu6                168                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu7                176                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total              1468                       # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu0             5045                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1             5065                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2             5031                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu3             5104                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu4             5070                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu5             5000                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu6             5035                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu7             4882                       # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total           40232                       # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0          1637                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1          1590                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2          1612                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu3          1603                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu4          1580                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu5          1621                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu6          1619                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu7          1576                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        12838                       # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0           5471                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1           5736                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2           5393                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu3           5491                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu4           5544                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu5           5435                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu6           5742                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu7           5581                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total         44393                       # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu0             10516                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1             10801                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2             10424                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu3             10595                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu4             10614                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu5             10435                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu6             10777                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu7             10463                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total            84625                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0            10516                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1            10801                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2            10424                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu3            10595                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu4            10614                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu5            10435                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu6            10777                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu7            10463                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total           84625                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu0    201814482                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1    202614244                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2    201254484                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu3    204173248                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu4    202773617                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu5    200011523                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu6    201333402                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu7    195252416                       # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total   1609227416                       # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu0     65483665                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1     63563227                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2     64483276                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu3     64122909                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu4     63203179                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu5     64843827                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu6     64763487                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu7     63043487                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total    513507057                       # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0    218853383                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1    229413457                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2    215692606                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu3    219654421                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu4    221773547                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu5    217413717                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu6    229694076                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu7    223253131                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total   1775748338                       # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0    420667865                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1    432027701                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2    416947090                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu3    423827669                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu4    424547164                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu5    417425240                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu6    431027478                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu7    418505547                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total   3384975754                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0    420667865                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1    432027701                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2    416947090                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu3    423827669                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu4    424547164                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu5    417425240                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu6    431027478                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu7    418505547                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total   3384975754                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    400422345                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    391061487                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    401502890                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    396621827                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    400743471                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    404102628                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    391101960                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    403583386                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   3189139994                       # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    215688086                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    217048117                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    213007261                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    216128145                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    218848364                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    214487951                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    216767566                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    211927994                       # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total   1723903484                       # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0    616110431                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1    608109604                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2    614510151                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu3    612749972                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu4    619591835                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu5    618590579                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu6    607869526                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu7    615511380                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   4913043478                       # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0      0.322797                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1      0.325598                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2      0.319388                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu3      0.325261                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu4      0.325355                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu5      0.322622                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu6      0.319987                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu7      0.315803                       # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total     0.322103                       # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.779153                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.788299                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.781386                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.773275                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.783730                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.775969                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.794017                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.790768                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.783235                       # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.653800                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.664889                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.644556                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.661327                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.657963                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.644263                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.661368                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.652291                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.655102                       # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu0       0.438221                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1       0.446636                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2       0.432190                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3       0.441550                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu4       0.442084                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu5       0.435991                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu6       0.441373                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu7       0.435686                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.439225                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0      0.438221                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1      0.446636                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2      0.432190                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3      0.441550                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu4      0.442084                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu5      0.435991                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu6      0.441373                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu7      0.435686                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.439225                       # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40002.595611                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857                       # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 39998.692981                       # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40001.814722                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39998.991821                       # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40002.626298                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000.638344                       # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.611515                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 39999.713489                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.611515                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 39999.713489                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cpu0.num_reads                           99815                       # number of read accesses completed
system.cpu0.num_writes                          53929                       # number of write accesses completed
system.cpu0.num_copies                              0                       # number of copy accesses completed
system.cpu0.l1c.replacements                    27826                       # number of replacements
system.cpu0.l1c.tagsinuse                  347.331950                       # Cycle average of tags in use
system.cpu0.l1c.total_refs                      11604                       # Total number of references to valid blocks.
system.cpu0.l1c.sampled_refs                    28187                       # Sample count of references to valid blocks.
system.cpu0.l1c.avg_refs                     0.411679                       # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu0.l1c.occ_blocks::cpu0           347.331950                       # Average occupied blocks per requestor
system.cpu0.l1c.occ_percent::cpu0            0.678383                       # Average percentage of cache occupancy
system.cpu0.l1c.occ_percent::total           0.678383                       # Average percentage of cache occupancy
system.cpu0.l1c.ReadReq_hits::cpu0               7530                       # number of ReadReq hits
system.cpu0.l1c.ReadReq_hits::total              7530                       # number of ReadReq hits
system.cpu0.l1c.WriteReq_hits::cpu0              1059                       # number of WriteReq hits
system.cpu0.l1c.WriteReq_hits::total             1059                       # number of WriteReq hits
system.cpu0.l1c.demand_hits::cpu0                8589                       # number of demand (read+write) hits
system.cpu0.l1c.demand_hits::total               8589                       # number of demand (read+write) hits
system.cpu0.l1c.overall_hits::cpu0               8589                       # number of overall hits
system.cpu0.l1c.overall_hits::total              8589                       # number of overall hits
system.cpu0.l1c.ReadReq_misses::cpu0            37279                       # number of ReadReq misses
system.cpu0.l1c.ReadReq_misses::total           37279                       # number of ReadReq misses
system.cpu0.l1c.WriteReq_misses::cpu0           23202                       # number of WriteReq misses
system.cpu0.l1c.WriteReq_misses::total          23202                       # number of WriteReq misses
system.cpu0.l1c.demand_misses::cpu0             60481                       # number of demand (read+write) misses
system.cpu0.l1c.demand_misses::total            60481                       # number of demand (read+write) misses
system.cpu0.l1c.overall_misses::cpu0            60481                       # number of overall misses
system.cpu0.l1c.overall_misses::total           60481                       # number of overall misses
system.cpu0.l1c.ReadReq_miss_latency::cpu0   1299667421                       # number of ReadReq miss cycles
system.cpu0.l1c.ReadReq_miss_latency::total   1299667421                       # number of ReadReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::cpu0   1001508092                       # number of WriteReq miss cycles
system.cpu0.l1c.WriteReq_miss_latency::total   1001508092                       # number of WriteReq miss cycles
system.cpu0.l1c.demand_miss_latency::cpu0   2301175513                       # number of demand (read+write) miss cycles
system.cpu0.l1c.demand_miss_latency::total   2301175513                       # number of demand (read+write) miss cycles
system.cpu0.l1c.overall_miss_latency::cpu0   2301175513                       # number of overall miss cycles
system.cpu0.l1c.overall_miss_latency::total   2301175513                       # number of overall miss cycles
system.cpu0.l1c.ReadReq_accesses::cpu0          44809                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.ReadReq_accesses::total         44809                       # number of ReadReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::cpu0         24261                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.WriteReq_accesses::total        24261                       # number of WriteReq accesses(hits+misses)
system.cpu0.l1c.demand_accesses::cpu0           69070                       # number of demand (read+write) accesses
system.cpu0.l1c.demand_accesses::total          69070                       # number of demand (read+write) accesses
system.cpu0.l1c.overall_accesses::cpu0          69070                       # number of overall (read+write) accesses
system.cpu0.l1c.overall_accesses::total         69070                       # number of overall (read+write) accesses
system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.831953                       # miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_miss_rate::total     0.831953                       # miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.956350                       # miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_miss_rate::total     0.956350                       # miss rate for WriteReq accesses
system.cpu0.l1c.demand_miss_rate::cpu0       0.875648                       # miss rate for demand accesses
system.cpu0.l1c.demand_miss_rate::total      0.875648                       # miss rate for demand accesses
system.cpu0.l1c.overall_miss_rate::cpu0      0.875648                       # miss rate for overall accesses
system.cpu0.l1c.overall_miss_rate::total     0.875648                       # miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698                       # average ReadReq miss latency
system.cpu0.l1c.ReadReq_avg_miss_latency::total 34863.258698                       # average ReadReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144                       # average WriteReq miss latency
system.cpu0.l1c.WriteReq_avg_miss_latency::total 43164.731144                       # average WriteReq miss latency
system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822                       # average overall miss latency
system.cpu0.l1c.demand_avg_miss_latency::total 38047.907822                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822                       # average overall miss latency
system.cpu0.l1c.overall_avg_miss_latency::total 38047.907822                       # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs    253845135                       # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs               69110                       # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3673.059398                       # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu0.l1c.writebacks::writebacks          11972                       # number of writebacks
system.cpu0.l1c.writebacks::total               11972                       # number of writebacks
system.cpu0.l1c.ReadReq_mshr_misses::cpu0        37279                       # number of ReadReq MSHR misses
system.cpu0.l1c.ReadReq_mshr_misses::total        37279                       # number of ReadReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23202                       # number of WriteReq MSHR misses
system.cpu0.l1c.WriteReq_mshr_misses::total        23202                       # number of WriteReq MSHR misses
system.cpu0.l1c.demand_mshr_misses::cpu0        60481                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.demand_mshr_misses::total        60481                       # number of demand (read+write) MSHR misses
system.cpu0.l1c.overall_mshr_misses::cpu0        60481                       # number of overall MSHR misses
system.cpu0.l1c.overall_mshr_misses::total        60481                       # number of overall MSHR misses
system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   1262244251                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_miss_latency::total   1262244251                       # number of ReadReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    978215253                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.WriteReq_mshr_miss_latency::total    978215253                       # number of WriteReq MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::cpu0   2240459504                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.demand_mshr_miss_latency::total   2240459504                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::cpu0   2240459504                       # number of overall MSHR miss cycles
system.cpu0.l1c.overall_mshr_miss_latency::total   2240459504                       # number of overall MSHR miss cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    894578632                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    894578632                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    569723237                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    569723237                       # number of WriteReq MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1464301869                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1464301869                       # number of overall MSHR uncacheable cycles
system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.831953                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.ReadReq_mshr_miss_rate::total     0.831953                       # mshr miss rate for ReadReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.956350                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.WriteReq_mshr_miss_rate::total     0.956350                       # mshr miss rate for WriteReq accesses
system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.875648                       # mshr miss rate for demand accesses
system.cpu0.l1c.demand_mshr_miss_rate::total     0.875648                       # mshr miss rate for demand accesses
system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.875648                       # mshr miss rate for overall accesses
system.cpu0.l1c.overall_mshr_miss_rate::total     0.875648                       # mshr miss rate for overall accesses
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373                       # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 33859.391373                       # average ReadReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007                       # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 42160.816007                       # average WriteReq mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156                       # average overall mshr miss latency
system.cpu0.l1c.demand_avg_mshr_miss_latency::total 37044.022156                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156                       # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_miss_latency::total 37044.022156                       # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu1.num_reads                           98493                       # number of read accesses completed
system.cpu1.num_writes                          53671                       # number of write accesses completed
system.cpu1.num_copies                              0                       # number of copy accesses completed
system.cpu1.l1c.replacements                    27684                       # number of replacements
system.cpu1.l1c.tagsinuse                  345.656340                       # Cycle average of tags in use
system.cpu1.l1c.total_refs                      11419                       # Total number of references to valid blocks.
system.cpu1.l1c.sampled_refs                    28039                       # Sample count of references to valid blocks.
system.cpu1.l1c.avg_refs                     0.407254                       # Average number of references to valid blocks.
system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu1.l1c.occ_blocks::cpu1           345.656340                       # Average occupied blocks per requestor
system.cpu1.l1c.occ_percent::cpu1            0.675110                       # Average percentage of cache occupancy
system.cpu1.l1c.occ_percent::total           0.675110                       # Average percentage of cache occupancy
system.cpu1.l1c.ReadReq_hits::cpu1               7429                       # number of ReadReq hits
system.cpu1.l1c.ReadReq_hits::total              7429                       # number of ReadReq hits
system.cpu1.l1c.WriteReq_hits::cpu1              1066                       # number of WriteReq hits
system.cpu1.l1c.WriteReq_hits::total             1066                       # number of WriteReq hits
system.cpu1.l1c.demand_hits::cpu1                8495                       # number of demand (read+write) hits
system.cpu1.l1c.demand_hits::total               8495                       # number of demand (read+write) hits
system.cpu1.l1c.overall_hits::cpu1               8495                       # number of overall hits
system.cpu1.l1c.overall_hits::total              8495                       # number of overall hits
system.cpu1.l1c.ReadReq_misses::cpu1            37110                       # number of ReadReq misses
system.cpu1.l1c.ReadReq_misses::total           37110                       # number of ReadReq misses
system.cpu1.l1c.WriteReq_misses::cpu1           23275                       # number of WriteReq misses
system.cpu1.l1c.WriteReq_misses::total          23275                       # number of WriteReq misses
system.cpu1.l1c.demand_misses::cpu1             60385                       # number of demand (read+write) misses
system.cpu1.l1c.demand_misses::total            60385                       # number of demand (read+write) misses
system.cpu1.l1c.overall_misses::cpu1            60385                       # number of overall misses
system.cpu1.l1c.overall_misses::total           60385                       # number of overall misses
system.cpu1.l1c.ReadReq_miss_latency::cpu1   1301760811                       # number of ReadReq miss cycles
system.cpu1.l1c.ReadReq_miss_latency::total   1301760811                       # number of ReadReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::cpu1   1014297005                       # number of WriteReq miss cycles
system.cpu1.l1c.WriteReq_miss_latency::total   1014297005                       # number of WriteReq miss cycles
system.cpu1.l1c.demand_miss_latency::cpu1   2316057816                       # number of demand (read+write) miss cycles
system.cpu1.l1c.demand_miss_latency::total   2316057816                       # number of demand (read+write) miss cycles
system.cpu1.l1c.overall_miss_latency::cpu1   2316057816                       # number of overall miss cycles
system.cpu1.l1c.overall_miss_latency::total   2316057816                       # number of overall miss cycles
system.cpu1.l1c.ReadReq_accesses::cpu1          44539                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.ReadReq_accesses::total         44539                       # number of ReadReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::cpu1         24341                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.WriteReq_accesses::total        24341                       # number of WriteReq accesses(hits+misses)
system.cpu1.l1c.demand_accesses::cpu1           68880                       # number of demand (read+write) accesses
system.cpu1.l1c.demand_accesses::total          68880                       # number of demand (read+write) accesses
system.cpu1.l1c.overall_accesses::cpu1          68880                       # number of overall (read+write) accesses
system.cpu1.l1c.overall_accesses::total         68880                       # number of overall (read+write) accesses
system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.833202                       # miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_miss_rate::total     0.833202                       # miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.956206                       # miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_miss_rate::total     0.956206                       # miss rate for WriteReq accesses
system.cpu1.l1c.demand_miss_rate::cpu1       0.876670                       # miss rate for demand accesses
system.cpu1.l1c.demand_miss_rate::total      0.876670                       # miss rate for demand accesses
system.cpu1.l1c.overall_miss_rate::cpu1      0.876670                       # miss rate for overall accesses
system.cpu1.l1c.overall_miss_rate::total     0.876670                       # miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375                       # average ReadReq miss latency
system.cpu1.l1c.ReadReq_avg_miss_latency::total 35078.437375                       # average ReadReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690                       # average WriteReq miss latency
system.cpu1.l1c.WriteReq_avg_miss_latency::total 43578.818690                       # average WriteReq miss latency
system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291                       # average overall miss latency
system.cpu1.l1c.demand_avg_miss_latency::total 38354.853291                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291                       # average overall miss latency
system.cpu1.l1c.overall_avg_miss_latency::total 38354.853291                       # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs    253325402                       # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs               68822                       # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3680.878237                       # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu1.l1c.writebacks::writebacks          11809                       # number of writebacks
system.cpu1.l1c.writebacks::total               11809                       # number of writebacks
system.cpu1.l1c.ReadReq_mshr_misses::cpu1        37110                       # number of ReadReq MSHR misses
system.cpu1.l1c.ReadReq_mshr_misses::total        37110                       # number of ReadReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23275                       # number of WriteReq MSHR misses
system.cpu1.l1c.WriteReq_mshr_misses::total        23275                       # number of WriteReq MSHR misses
system.cpu1.l1c.demand_mshr_misses::cpu1        60385                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.demand_mshr_misses::total        60385                       # number of demand (read+write) MSHR misses
system.cpu1.l1c.overall_mshr_misses::cpu1        60385                       # number of overall MSHR misses
system.cpu1.l1c.overall_mshr_misses::total        60385                       # number of overall MSHR misses
system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   1264508347                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_miss_latency::total   1264508347                       # number of ReadReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    990933889                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.WriteReq_mshr_miss_latency::total    990933889                       # number of WriteReq MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::cpu1   2255442236                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.demand_mshr_miss_latency::total   2255442236                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::cpu1   2255442236                       # number of overall MSHR miss cycles
system.cpu1.l1c.overall_mshr_miss_latency::total   2255442236                       # number of overall MSHR miss cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    877119159                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    877119159                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    578327433                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    578327433                       # number of WriteReq MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1455446592                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1455446592                       # number of overall MSHR uncacheable cycles
system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.833202                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.ReadReq_mshr_miss_rate::total     0.833202                       # mshr miss rate for ReadReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.956206                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.WriteReq_mshr_miss_rate::total     0.956206                       # mshr miss rate for WriteReq accesses
system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.876670                       # mshr miss rate for demand accesses
system.cpu1.l1c.demand_mshr_miss_rate::total     0.876670                       # mshr miss rate for demand accesses
system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.876670                       # mshr miss rate for overall accesses
system.cpu1.l1c.overall_mshr_miss_rate::total     0.876670                       # mshr miss rate for overall accesses
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410                       # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 34074.598410                       # average ReadReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825                       # average WriteReq mshr miss latency
system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 42575.032825                       # average WriteReq mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793                       # average overall mshr miss latency
system.cpu1.l1c.demand_avg_mshr_miss_latency::total 37351.034793                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793                       # average overall mshr miss latency
system.cpu1.l1c.overall_avg_mshr_miss_latency::total 37351.034793                       # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu2.num_reads                           99149                       # number of read accesses completed
system.cpu2.num_writes                          53185                       # number of write accesses completed
system.cpu2.num_copies                              0                       # number of copy accesses completed
system.cpu2.l1c.replacements                    27627                       # number of replacements
system.cpu2.l1c.tagsinuse                  345.430231                       # Cycle average of tags in use
system.cpu2.l1c.total_refs                      11519                       # Total number of references to valid blocks.
system.cpu2.l1c.sampled_refs                    27982                       # Sample count of references to valid blocks.
system.cpu2.l1c.avg_refs                     0.411657                       # Average number of references to valid blocks.
system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu2.l1c.occ_blocks::cpu2           345.430231                       # Average occupied blocks per requestor
system.cpu2.l1c.occ_percent::cpu2            0.674668                       # Average percentage of cache occupancy
system.cpu2.l1c.occ_percent::total           0.674668                       # Average percentage of cache occupancy
system.cpu2.l1c.ReadReq_hits::cpu2               7576                       # number of ReadReq hits
system.cpu2.l1c.ReadReq_hits::total              7576                       # number of ReadReq hits
system.cpu2.l1c.WriteReq_hits::cpu2              1069                       # number of WriteReq hits
system.cpu2.l1c.WriteReq_hits::total             1069                       # number of WriteReq hits
system.cpu2.l1c.demand_hits::cpu2                8645                       # number of demand (read+write) hits
system.cpu2.l1c.demand_hits::total               8645                       # number of demand (read+write) hits
system.cpu2.l1c.overall_hits::cpu2               8645                       # number of overall hits
system.cpu2.l1c.overall_hits::total              8645                       # number of overall hits
system.cpu2.l1c.ReadReq_misses::cpu2            37144                       # number of ReadReq misses
system.cpu2.l1c.ReadReq_misses::total           37144                       # number of ReadReq misses
system.cpu2.l1c.WriteReq_misses::cpu2           22885                       # number of WriteReq misses
system.cpu2.l1c.WriteReq_misses::total          22885                       # number of WriteReq misses
system.cpu2.l1c.demand_misses::cpu2             60029                       # number of demand (read+write) misses
system.cpu2.l1c.demand_misses::total            60029                       # number of demand (read+write) misses
system.cpu2.l1c.overall_misses::cpu2            60029                       # number of overall misses
system.cpu2.l1c.overall_misses::total           60029                       # number of overall misses
system.cpu2.l1c.ReadReq_miss_latency::cpu2   1302790562                       # number of ReadReq miss cycles
system.cpu2.l1c.ReadReq_miss_latency::total   1302790562                       # number of ReadReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::cpu2    991654869                       # number of WriteReq miss cycles
system.cpu2.l1c.WriteReq_miss_latency::total    991654869                       # number of WriteReq miss cycles
system.cpu2.l1c.demand_miss_latency::cpu2   2294445431                       # number of demand (read+write) miss cycles
system.cpu2.l1c.demand_miss_latency::total   2294445431                       # number of demand (read+write) miss cycles
system.cpu2.l1c.overall_miss_latency::cpu2   2294445431                       # number of overall miss cycles
system.cpu2.l1c.overall_miss_latency::total   2294445431                       # number of overall miss cycles
system.cpu2.l1c.ReadReq_accesses::cpu2          44720                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.ReadReq_accesses::total         44720                       # number of ReadReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::cpu2         23954                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.WriteReq_accesses::total        23954                       # number of WriteReq accesses(hits+misses)
system.cpu2.l1c.demand_accesses::cpu2           68674                       # number of demand (read+write) accesses
system.cpu2.l1c.demand_accesses::total          68674                       # number of demand (read+write) accesses
system.cpu2.l1c.overall_accesses::cpu2          68674                       # number of overall (read+write) accesses
system.cpu2.l1c.overall_accesses::total         68674                       # number of overall (read+write) accesses
system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.830590                       # miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_miss_rate::total     0.830590                       # miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955373                       # miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_miss_rate::total     0.955373                       # miss rate for WriteReq accesses
system.cpu2.l1c.demand_miss_rate::cpu2       0.874115                       # miss rate for demand accesses
system.cpu2.l1c.demand_miss_rate::total      0.874115                       # miss rate for demand accesses
system.cpu2.l1c.overall_miss_rate::cpu2      0.874115                       # miss rate for overall accesses
system.cpu2.l1c.overall_miss_rate::total     0.874115                       # miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314                       # average ReadReq miss latency
system.cpu2.l1c.ReadReq_avg_miss_latency::total 35074.051314                       # average ReadReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535                       # average WriteReq miss latency
system.cpu2.l1c.WriteReq_avg_miss_latency::total 43332.089535                       # average WriteReq miss latency
system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080                       # average overall miss latency
system.cpu2.l1c.demand_avg_miss_latency::total 38222.283080                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080                       # average overall miss latency
system.cpu2.l1c.overall_avg_miss_latency::total 38222.283080                       # average overall miss latency
system.cpu2.l1c.blocked_cycles::no_mshrs    254303447                       # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_mshrs               68698                       # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3701.759105                       # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu2.l1c.writebacks::writebacks          11784                       # number of writebacks
system.cpu2.l1c.writebacks::total               11784                       # number of writebacks
system.cpu2.l1c.ReadReq_mshr_misses::cpu2        37144                       # number of ReadReq MSHR misses
system.cpu2.l1c.ReadReq_mshr_misses::total        37144                       # number of ReadReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::cpu2        22885                       # number of WriteReq MSHR misses
system.cpu2.l1c.WriteReq_mshr_misses::total        22885                       # number of WriteReq MSHR misses
system.cpu2.l1c.demand_mshr_misses::cpu2        60029                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.demand_mshr_misses::total        60029                       # number of demand (read+write) MSHR misses
system.cpu2.l1c.overall_mshr_misses::cpu2        60029                       # number of overall MSHR misses
system.cpu2.l1c.overall_mshr_misses::total        60029                       # number of overall MSHR misses
system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   1265501937                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_miss_latency::total   1265501937                       # number of ReadReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    968684322                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.WriteReq_mshr_miss_latency::total    968684322                       # number of WriteReq MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::cpu2   2234186259                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.demand_mshr_miss_latency::total   2234186259                       # number of demand (read+write) MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::cpu2   2234186259                       # number of overall MSHR miss cycles
system.cpu2.l1c.overall_mshr_miss_latency::total   2234186259                       # number of overall MSHR miss cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    900513056                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    900513056                       # number of ReadReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    566349170                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    566349170                       # number of WriteReq MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1466862226                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1466862226                       # number of overall MSHR uncacheable cycles
system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.830590                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.ReadReq_mshr_miss_rate::total     0.830590                       # mshr miss rate for ReadReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955373                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.WriteReq_mshr_miss_rate::total     0.955373                       # mshr miss rate for WriteReq accesses
system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.874115                       # mshr miss rate for demand accesses
system.cpu2.l1c.demand_mshr_miss_rate::total     0.874115                       # mshr miss rate for demand accesses
system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.874115                       # mshr miss rate for overall accesses
system.cpu2.l1c.overall_mshr_miss_rate::total     0.874115                       # mshr miss rate for overall accesses
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684                       # average ReadReq mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 34070.157684                       # average ReadReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409                       # average WriteReq mshr miss latency
system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 42328.351409                       # average WriteReq mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733                       # average overall mshr miss latency
system.cpu2.l1c.demand_avg_mshr_miss_latency::total 37218.448733                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733                       # average overall mshr miss latency
system.cpu2.l1c.overall_avg_mshr_miss_latency::total 37218.448733                       # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu3.num_reads                           99588                       # number of read accesses completed
system.cpu3.num_writes                          53645                       # number of write accesses completed
system.cpu3.num_copies                              0                       # number of copy accesses completed
system.cpu3.l1c.replacements                    27837                       # number of replacements
system.cpu3.l1c.tagsinuse                  347.574885                       # Cycle average of tags in use
system.cpu3.l1c.total_refs                      11563                       # Total number of references to valid blocks.
system.cpu3.l1c.sampled_refs                    28190                       # Sample count of references to valid blocks.
system.cpu3.l1c.avg_refs                     0.410181                       # Average number of references to valid blocks.
system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu3.l1c.occ_blocks::cpu3           347.574885                       # Average occupied blocks per requestor
system.cpu3.l1c.occ_percent::cpu3            0.678857                       # Average percentage of cache occupancy
system.cpu3.l1c.occ_percent::total           0.678857                       # Average percentage of cache occupancy
system.cpu3.l1c.ReadReq_hits::cpu3               7552                       # number of ReadReq hits
system.cpu3.l1c.ReadReq_hits::total              7552                       # number of ReadReq hits
system.cpu3.l1c.WriteReq_hits::cpu3              1078                       # number of WriteReq hits
system.cpu3.l1c.WriteReq_hits::total             1078                       # number of WriteReq hits
system.cpu3.l1c.demand_hits::cpu3                8630                       # number of demand (read+write) hits
system.cpu3.l1c.demand_hits::total               8630                       # number of demand (read+write) hits
system.cpu3.l1c.overall_hits::cpu3               8630                       # number of overall hits
system.cpu3.l1c.overall_hits::total              8630                       # number of overall hits
system.cpu3.l1c.ReadReq_misses::cpu3            37191                       # number of ReadReq misses
system.cpu3.l1c.ReadReq_misses::total           37191                       # number of ReadReq misses
system.cpu3.l1c.WriteReq_misses::cpu3           23219                       # number of WriteReq misses
system.cpu3.l1c.WriteReq_misses::total          23219                       # number of WriteReq misses
system.cpu3.l1c.demand_misses::cpu3             60410                       # number of demand (read+write) misses
system.cpu3.l1c.demand_misses::total            60410                       # number of demand (read+write) misses
system.cpu3.l1c.overall_misses::cpu3            60410                       # number of overall misses
system.cpu3.l1c.overall_misses::total           60410                       # number of overall misses
system.cpu3.l1c.ReadReq_miss_latency::cpu3   1312024933                       # number of ReadReq miss cycles
system.cpu3.l1c.ReadReq_miss_latency::total   1312024933                       # number of ReadReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::cpu3    995527685                       # number of WriteReq miss cycles
system.cpu3.l1c.WriteReq_miss_latency::total    995527685                       # number of WriteReq miss cycles
system.cpu3.l1c.demand_miss_latency::cpu3   2307552618                       # number of demand (read+write) miss cycles
system.cpu3.l1c.demand_miss_latency::total   2307552618                       # number of demand (read+write) miss cycles
system.cpu3.l1c.overall_miss_latency::cpu3   2307552618                       # number of overall miss cycles
system.cpu3.l1c.overall_miss_latency::total   2307552618                       # number of overall miss cycles
system.cpu3.l1c.ReadReq_accesses::cpu3          44743                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.ReadReq_accesses::total         44743                       # number of ReadReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::cpu3         24297                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.WriteReq_accesses::total        24297                       # number of WriteReq accesses(hits+misses)
system.cpu3.l1c.demand_accesses::cpu3           69040                       # number of demand (read+write) accesses
system.cpu3.l1c.demand_accesses::total          69040                       # number of demand (read+write) accesses
system.cpu3.l1c.overall_accesses::cpu3          69040                       # number of overall (read+write) accesses
system.cpu3.l1c.overall_accesses::total         69040                       # number of overall (read+write) accesses
system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.831214                       # miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_miss_rate::total     0.831214                       # miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.955632                       # miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_miss_rate::total     0.955632                       # miss rate for WriteReq accesses
system.cpu3.l1c.demand_miss_rate::cpu3       0.875000                       # miss rate for demand accesses
system.cpu3.l1c.demand_miss_rate::total      0.875000                       # miss rate for demand accesses
system.cpu3.l1c.overall_miss_rate::cpu3      0.875000                       # miss rate for overall accesses
system.cpu3.l1c.overall_miss_rate::total     0.875000                       # miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452                       # average ReadReq miss latency
system.cpu3.l1c.ReadReq_avg_miss_latency::total 35278.022452                       # average ReadReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470                       # average WriteReq miss latency
system.cpu3.l1c.WriteReq_avg_miss_latency::total 42875.562470                       # average WriteReq miss latency
system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340                       # average overall miss latency
system.cpu3.l1c.demand_avg_miss_latency::total 38198.189340                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340                       # average overall miss latency
system.cpu3.l1c.overall_avg_miss_latency::total 38198.189340                       # average overall miss latency
system.cpu3.l1c.blocked_cycles::no_mshrs    254462667                       # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_mshrs               68939                       # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3691.127910                       # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu3.l1c.writebacks::writebacks          11956                       # number of writebacks
system.cpu3.l1c.writebacks::total               11956                       # number of writebacks
system.cpu3.l1c.ReadReq_mshr_misses::cpu3        37191                       # number of ReadReq MSHR misses
system.cpu3.l1c.ReadReq_mshr_misses::total        37191                       # number of ReadReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23219                       # number of WriteReq MSHR misses
system.cpu3.l1c.WriteReq_mshr_misses::total        23219                       # number of WriteReq MSHR misses
system.cpu3.l1c.demand_mshr_misses::cpu3        60410                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.demand_mshr_misses::total        60410                       # number of demand (read+write) MSHR misses
system.cpu3.l1c.overall_mshr_misses::cpu3        60410                       # number of overall MSHR misses
system.cpu3.l1c.overall_mshr_misses::total        60410                       # number of overall MSHR misses
system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   1274692143                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_miss_latency::total   1274692143                       # number of ReadReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    972218785                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.WriteReq_mshr_miss_latency::total    972218785                       # number of WriteReq MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::cpu3   2246910928                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.demand_mshr_miss_latency::total   2246910928                       # number of demand (read+write) MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::cpu3   2246910928                       # number of overall MSHR miss cycles
system.cpu3.l1c.overall_mshr_miss_latency::total   2246910928                       # number of overall MSHR miss cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    889431937                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    889431937                       # number of ReadReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    569772276                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    569772276                       # number of WriteReq MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1459204213                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1459204213                       # number of overall MSHR uncacheable cycles
system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.831214                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.ReadReq_mshr_miss_rate::total     0.831214                       # mshr miss rate for ReadReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.955632                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.WriteReq_mshr_miss_rate::total     0.955632                       # mshr miss rate for WriteReq accesses
system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.875000                       # mshr miss rate for demand accesses
system.cpu3.l1c.demand_mshr_miss_rate::total     0.875000                       # mshr miss rate for demand accesses
system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.875000                       # mshr miss rate for overall accesses
system.cpu3.l1c.overall_mshr_miss_rate::total     0.875000                       # mshr miss rate for overall accesses
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970                       # average ReadReq mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34274.209970                       # average ReadReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641                       # average WriteReq mshr miss latency
system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 41871.690641                       # average WriteReq mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047                       # average overall mshr miss latency
system.cpu3.l1c.demand_avg_mshr_miss_latency::total 37194.354047                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047                       # average overall mshr miss latency
system.cpu3.l1c.overall_avg_mshr_miss_latency::total 37194.354047                       # average overall mshr miss latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu4.num_reads                           99725                       # number of read accesses completed
system.cpu4.num_writes                          53533                       # number of write accesses completed
system.cpu4.num_copies                              0                       # number of copy accesses completed
system.cpu4.l1c.replacements                    27683                       # number of replacements
system.cpu4.l1c.tagsinuse                  347.631602                       # Cycle average of tags in use
system.cpu4.l1c.total_refs                      11724                       # Total number of references to valid blocks.
system.cpu4.l1c.sampled_refs                    28041                       # Sample count of references to valid blocks.
system.cpu4.l1c.avg_refs                     0.418102                       # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu4.l1c.occ_blocks::cpu4           347.631602                       # Average occupied blocks per requestor
system.cpu4.l1c.occ_percent::cpu4            0.678968                       # Average percentage of cache occupancy
system.cpu4.l1c.occ_percent::total           0.678968                       # Average percentage of cache occupancy
system.cpu4.l1c.ReadReq_hits::cpu4               7686                       # number of ReadReq hits
system.cpu4.l1c.ReadReq_hits::total              7686                       # number of ReadReq hits
system.cpu4.l1c.WriteReq_hits::cpu4              1123                       # number of WriteReq hits
system.cpu4.l1c.WriteReq_hits::total             1123                       # number of WriteReq hits
system.cpu4.l1c.demand_hits::cpu4                8809                       # number of demand (read+write) hits
system.cpu4.l1c.demand_hits::total               8809                       # number of demand (read+write) hits
system.cpu4.l1c.overall_hits::cpu4               8809                       # number of overall hits
system.cpu4.l1c.overall_hits::total              8809                       # number of overall hits
system.cpu4.l1c.ReadReq_misses::cpu4            37251                       # number of ReadReq misses
system.cpu4.l1c.ReadReq_misses::total           37251                       # number of ReadReq misses
system.cpu4.l1c.WriteReq_misses::cpu4           22937                       # number of WriteReq misses
system.cpu4.l1c.WriteReq_misses::total          22937                       # number of WriteReq misses
system.cpu4.l1c.demand_misses::cpu4             60188                       # number of demand (read+write) misses
system.cpu4.l1c.demand_misses::total            60188                       # number of demand (read+write) misses
system.cpu4.l1c.overall_misses::cpu4            60188                       # number of overall misses
system.cpu4.l1c.overall_misses::total           60188                       # number of overall misses
system.cpu4.l1c.ReadReq_miss_latency::cpu4   1303112178                       # number of ReadReq miss cycles
system.cpu4.l1c.ReadReq_miss_latency::total   1303112178                       # number of ReadReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::cpu4    994450363                       # number of WriteReq miss cycles
system.cpu4.l1c.WriteReq_miss_latency::total    994450363                       # number of WriteReq miss cycles
system.cpu4.l1c.demand_miss_latency::cpu4   2297562541                       # number of demand (read+write) miss cycles
system.cpu4.l1c.demand_miss_latency::total   2297562541                       # number of demand (read+write) miss cycles
system.cpu4.l1c.overall_miss_latency::cpu4   2297562541                       # number of overall miss cycles
system.cpu4.l1c.overall_miss_latency::total   2297562541                       # number of overall miss cycles
system.cpu4.l1c.ReadReq_accesses::cpu4          44937                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.ReadReq_accesses::total         44937                       # number of ReadReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::cpu4         24060                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.WriteReq_accesses::total        24060                       # number of WriteReq accesses(hits+misses)
system.cpu4.l1c.demand_accesses::cpu4           68997                       # number of demand (read+write) accesses
system.cpu4.l1c.demand_accesses::total          68997                       # number of demand (read+write) accesses
system.cpu4.l1c.overall_accesses::cpu4          68997                       # number of overall (read+write) accesses
system.cpu4.l1c.overall_accesses::total         68997                       # number of overall (read+write) accesses
system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.828961                       # miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_miss_rate::total     0.828961                       # miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.953325                       # miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_miss_rate::total     0.953325                       # miss rate for WriteReq accesses
system.cpu4.l1c.demand_miss_rate::cpu4       0.872328                       # miss rate for demand accesses
system.cpu4.l1c.demand_miss_rate::total      0.872328                       # miss rate for demand accesses
system.cpu4.l1c.overall_miss_rate::cpu4      0.872328                       # miss rate for overall accesses
system.cpu4.l1c.overall_miss_rate::total     0.872328                       # miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149                       # average ReadReq miss latency
system.cpu4.l1c.ReadReq_avg_miss_latency::total 34981.938149                       # average ReadReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302                       # average WriteReq miss latency
system.cpu4.l1c.WriteReq_avg_miss_latency::total 43355.729302                       # average WriteReq miss latency
system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970                       # average overall miss latency
system.cpu4.l1c.demand_avg_miss_latency::total 38173.099970                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970                       # average overall miss latency
system.cpu4.l1c.overall_avg_miss_latency::total 38173.099970                       # average overall miss latency
system.cpu4.l1c.blocked_cycles::no_mshrs    254136532                       # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_mshrs               68868                       # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3690.197653                       # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu4.l1c.writebacks::writebacks          11763                       # number of writebacks
system.cpu4.l1c.writebacks::total               11763                       # number of writebacks
system.cpu4.l1c.ReadReq_mshr_misses::cpu4        37251                       # number of ReadReq MSHR misses
system.cpu4.l1c.ReadReq_mshr_misses::total        37251                       # number of ReadReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::cpu4        22937                       # number of WriteReq MSHR misses
system.cpu4.l1c.WriteReq_mshr_misses::total        22937                       # number of WriteReq MSHR misses
system.cpu4.l1c.demand_mshr_misses::cpu4        60188                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.demand_mshr_misses::total        60188                       # number of demand (read+write) MSHR misses
system.cpu4.l1c.overall_mshr_misses::cpu4        60188                       # number of overall MSHR misses
system.cpu4.l1c.overall_mshr_misses::total        60188                       # number of overall MSHR misses
system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   1265717116                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_miss_latency::total   1265717116                       # number of ReadReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    971425596                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.WriteReq_mshr_miss_latency::total    971425596                       # number of WriteReq MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::cpu4   2237142712                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.demand_mshr_miss_latency::total   2237142712                       # number of demand (read+write) MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::cpu4   2237142712                       # number of overall MSHR miss cycles
system.cpu4.l1c.overall_mshr_miss_latency::total   2237142712                       # number of overall MSHR miss cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    898461911                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    898461911                       # number of ReadReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    576408625                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    576408625                       # number of WriteReq MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1474870536                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1474870536                       # number of overall MSHR uncacheable cycles
system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.828961                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.ReadReq_mshr_miss_rate::total     0.828961                       # mshr miss rate for ReadReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.953325                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.WriteReq_mshr_miss_rate::total     0.953325                       # mshr miss rate for WriteReq accesses
system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.872328                       # mshr miss rate for demand accesses
system.cpu4.l1c.demand_mshr_miss_rate::total     0.872328                       # mshr miss rate for demand accesses
system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.872328                       # mshr miss rate for overall accesses
system.cpu4.l1c.overall_mshr_miss_rate::total     0.872328                       # mshr miss rate for overall accesses
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817                       # average ReadReq mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 33978.070817                       # average ReadReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864                       # average WriteReq mshr miss latency
system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 42351.902864                       # average WriteReq mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222                       # average overall mshr miss latency
system.cpu4.l1c.demand_avg_mshr_miss_latency::total 37169.248222                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222                       # average overall mshr miss latency
system.cpu4.l1c.overall_avg_mshr_miss_latency::total 37169.248222                       # average overall mshr miss latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu5.num_reads                          100000                       # number of read accesses completed
system.cpu5.num_writes                          53710                       # number of write accesses completed
system.cpu5.num_copies                              0                       # number of copy accesses completed
system.cpu5.l1c.replacements                    27832                       # number of replacements
system.cpu5.l1c.tagsinuse                  346.806811                       # Cycle average of tags in use
system.cpu5.l1c.total_refs                      11748                       # Total number of references to valid blocks.
system.cpu5.l1c.sampled_refs                    28191                       # Sample count of references to valid blocks.
system.cpu5.l1c.avg_refs                     0.416729                       # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu5.l1c.occ_blocks::cpu5           346.806811                       # Average occupied blocks per requestor
system.cpu5.l1c.occ_percent::cpu5            0.677357                       # Average percentage of cache occupancy
system.cpu5.l1c.occ_percent::total           0.677357                       # Average percentage of cache occupancy
system.cpu5.l1c.ReadReq_hits::cpu5               7592                       # number of ReadReq hits
system.cpu5.l1c.ReadReq_hits::total              7592                       # number of ReadReq hits
system.cpu5.l1c.WriteReq_hits::cpu5              1126                       # number of WriteReq hits
system.cpu5.l1c.WriteReq_hits::total             1126                       # number of WriteReq hits
system.cpu5.l1c.demand_hits::cpu5                8718                       # number of demand (read+write) hits
system.cpu5.l1c.demand_hits::total               8718                       # number of demand (read+write) hits
system.cpu5.l1c.overall_hits::cpu5               8718                       # number of overall hits
system.cpu5.l1c.overall_hits::total              8718                       # number of overall hits
system.cpu5.l1c.ReadReq_misses::cpu5            37349                       # number of ReadReq misses
system.cpu5.l1c.ReadReq_misses::total           37349                       # number of ReadReq misses
system.cpu5.l1c.WriteReq_misses::cpu5           23013                       # number of WriteReq misses
system.cpu5.l1c.WriteReq_misses::total          23013                       # number of WriteReq misses
system.cpu5.l1c.demand_misses::cpu5             60362                       # number of demand (read+write) misses
system.cpu5.l1c.demand_misses::total            60362                       # number of demand (read+write) misses
system.cpu5.l1c.overall_misses::cpu5            60362                       # number of overall misses
system.cpu5.l1c.overall_misses::total           60362                       # number of overall misses
system.cpu5.l1c.ReadReq_miss_latency::cpu5   1291933371                       # number of ReadReq miss cycles
system.cpu5.l1c.ReadReq_miss_latency::total   1291933371                       # number of ReadReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::cpu5    998304045                       # number of WriteReq miss cycles
system.cpu5.l1c.WriteReq_miss_latency::total    998304045                       # number of WriteReq miss cycles
system.cpu5.l1c.demand_miss_latency::cpu5   2290237416                       # number of demand (read+write) miss cycles
system.cpu5.l1c.demand_miss_latency::total   2290237416                       # number of demand (read+write) miss cycles
system.cpu5.l1c.overall_miss_latency::cpu5   2290237416                       # number of overall miss cycles
system.cpu5.l1c.overall_miss_latency::total   2290237416                       # number of overall miss cycles
system.cpu5.l1c.ReadReq_accesses::cpu5          44941                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.ReadReq_accesses::total         44941                       # number of ReadReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::cpu5         24139                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.WriteReq_accesses::total        24139                       # number of WriteReq accesses(hits+misses)
system.cpu5.l1c.demand_accesses::cpu5           69080                       # number of demand (read+write) accesses
system.cpu5.l1c.demand_accesses::total          69080                       # number of demand (read+write) accesses
system.cpu5.l1c.overall_accesses::cpu5          69080                       # number of overall (read+write) accesses
system.cpu5.l1c.overall_accesses::total         69080                       # number of overall (read+write) accesses
system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.831067                       # miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_miss_rate::total     0.831067                       # miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.953353                       # miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_miss_rate::total     0.953353                       # miss rate for WriteReq accesses
system.cpu5.l1c.demand_miss_rate::cpu5       0.873798                       # miss rate for demand accesses
system.cpu5.l1c.demand_miss_rate::total      0.873798                       # miss rate for demand accesses
system.cpu5.l1c.overall_miss_rate::cpu5      0.873798                       # miss rate for overall accesses
system.cpu5.l1c.overall_miss_rate::total     0.873798                       # miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352                       # average ReadReq miss latency
system.cpu5.l1c.ReadReq_avg_miss_latency::total 34590.842352                       # average ReadReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563                       # average WriteReq miss latency
system.cpu5.l1c.WriteReq_avg_miss_latency::total 43380.004563                       # average WriteReq miss latency
system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625                       # average overall miss latency
system.cpu5.l1c.demand_avg_miss_latency::total 37941.708625                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625                       # average overall miss latency
system.cpu5.l1c.overall_avg_miss_latency::total 37941.708625                       # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs    253381114                       # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs               68969                       # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3673.840624                       # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu5.l1c.writebacks::writebacks          11908                       # number of writebacks
system.cpu5.l1c.writebacks::total               11908                       # number of writebacks
system.cpu5.l1c.ReadReq_mshr_misses::cpu5        37349                       # number of ReadReq MSHR misses
system.cpu5.l1c.ReadReq_mshr_misses::total        37349                       # number of ReadReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23013                       # number of WriteReq MSHR misses
system.cpu5.l1c.WriteReq_mshr_misses::total        23013                       # number of WriteReq MSHR misses
system.cpu5.l1c.demand_mshr_misses::cpu5        60362                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.demand_mshr_misses::total        60362                       # number of demand (read+write) MSHR misses
system.cpu5.l1c.overall_mshr_misses::cpu5        60362                       # number of overall MSHR misses
system.cpu5.l1c.overall_mshr_misses::total        60362                       # number of overall MSHR misses
system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   1254436910                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_miss_latency::total   1254436910                       # number of ReadReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    975203983                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.WriteReq_mshr_miss_latency::total    975203983                       # number of WriteReq MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::cpu5   2229640893                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.demand_mshr_miss_latency::total   2229640893                       # number of demand (read+write) MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::cpu5   2229640893                       # number of overall MSHR miss cycles
system.cpu5.l1c.overall_mshr_miss_latency::total   2229640893                       # number of overall MSHR miss cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    902856034                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    902856034                       # number of ReadReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    567587171                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    567587171                       # number of WriteReq MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1470443205                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1470443205                       # number of overall MSHR uncacheable cycles
system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.831067                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.ReadReq_mshr_miss_rate::total     0.831067                       # mshr miss rate for ReadReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.953353                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.WriteReq_mshr_miss_rate::total     0.953353                       # mshr miss rate for WriteReq accesses
system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.873798                       # mshr miss rate for demand accesses
system.cpu5.l1c.demand_mshr_miss_rate::total     0.873798                       # mshr miss rate for demand accesses
system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.873798                       # mshr miss rate for overall accesses
system.cpu5.l1c.overall_mshr_miss_rate::total     0.873798                       # mshr miss rate for overall accesses
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160                       # average ReadReq mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 33586.894160                       # average ReadReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397                       # average WriteReq mshr miss latency
system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 42376.221397                       # average WriteReq mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349                       # average overall mshr miss latency
system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36937.823349                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349                       # average overall mshr miss latency
system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36937.823349                       # average overall mshr miss latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu6.num_reads                           99389                       # number of read accesses completed
system.cpu6.num_writes                          53686                       # number of write accesses completed
system.cpu6.num_copies                              0                       # number of copy accesses completed
system.cpu6.l1c.replacements                    27861                       # number of replacements
system.cpu6.l1c.tagsinuse                  347.289326                       # Cycle average of tags in use
system.cpu6.l1c.total_refs                      11520                       # Total number of references to valid blocks.
system.cpu6.l1c.sampled_refs                    28198                       # Sample count of references to valid blocks.
system.cpu6.l1c.avg_refs                     0.408540                       # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu6.l1c.occ_blocks::cpu6           347.289326                       # Average occupied blocks per requestor
system.cpu6.l1c.occ_percent::cpu6            0.678299                       # Average percentage of cache occupancy
system.cpu6.l1c.occ_percent::total           0.678299                       # Average percentage of cache occupancy
system.cpu6.l1c.ReadReq_hits::cpu6               7543                       # number of ReadReq hits
system.cpu6.l1c.ReadReq_hits::total              7543                       # number of ReadReq hits
system.cpu6.l1c.WriteReq_hits::cpu6              1119                       # number of WriteReq hits
system.cpu6.l1c.WriteReq_hits::total             1119                       # number of WriteReq hits
system.cpu6.l1c.demand_hits::cpu6                8662                       # number of demand (read+write) hits
system.cpu6.l1c.demand_hits::total               8662                       # number of demand (read+write) hits
system.cpu6.l1c.overall_hits::cpu6               8662                       # number of overall hits
system.cpu6.l1c.overall_hits::total              8662                       # number of overall hits
system.cpu6.l1c.ReadReq_misses::cpu6            37109                       # number of ReadReq misses
system.cpu6.l1c.ReadReq_misses::total           37109                       # number of ReadReq misses
system.cpu6.l1c.WriteReq_misses::cpu6           23142                       # number of WriteReq misses
system.cpu6.l1c.WriteReq_misses::total          23142                       # number of WriteReq misses
system.cpu6.l1c.demand_misses::cpu6             60251                       # number of demand (read+write) misses
system.cpu6.l1c.demand_misses::total            60251                       # number of demand (read+write) misses
system.cpu6.l1c.overall_misses::cpu6            60251                       # number of overall misses
system.cpu6.l1c.overall_misses::total           60251                       # number of overall misses
system.cpu6.l1c.ReadReq_miss_latency::cpu6   1299799162                       # number of ReadReq miss cycles
system.cpu6.l1c.ReadReq_miss_latency::total   1299799162                       # number of ReadReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::cpu6   1015775810                       # number of WriteReq miss cycles
system.cpu6.l1c.WriteReq_miss_latency::total   1015775810                       # number of WriteReq miss cycles
system.cpu6.l1c.demand_miss_latency::cpu6   2315574972                       # number of demand (read+write) miss cycles
system.cpu6.l1c.demand_miss_latency::total   2315574972                       # number of demand (read+write) miss cycles
system.cpu6.l1c.overall_miss_latency::cpu6   2315574972                       # number of overall miss cycles
system.cpu6.l1c.overall_miss_latency::total   2315574972                       # number of overall miss cycles
system.cpu6.l1c.ReadReq_accesses::cpu6          44652                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.ReadReq_accesses::total         44652                       # number of ReadReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::cpu6         24261                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.WriteReq_accesses::total        24261                       # number of WriteReq accesses(hits+misses)
system.cpu6.l1c.demand_accesses::cpu6           68913                       # number of demand (read+write) accesses
system.cpu6.l1c.demand_accesses::total          68913                       # number of demand (read+write) accesses
system.cpu6.l1c.overall_accesses::cpu6          68913                       # number of overall (read+write) accesses
system.cpu6.l1c.overall_accesses::total         68913                       # number of overall (read+write) accesses
system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.831071                       # miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_miss_rate::total     0.831071                       # miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953877                       # miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_miss_rate::total     0.953877                       # miss rate for WriteReq accesses
system.cpu6.l1c.demand_miss_rate::cpu6       0.874305                       # miss rate for demand accesses
system.cpu6.l1c.demand_miss_rate::total      0.874305                       # miss rate for demand accesses
system.cpu6.l1c.overall_miss_rate::cpu6      0.874305                       # miss rate for overall accesses
system.cpu6.l1c.overall_miss_rate::total     0.874305                       # miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844                       # average ReadReq miss latency
system.cpu6.l1c.ReadReq_avg_miss_latency::total 35026.520844                       # average ReadReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019                       # average WriteReq miss latency
system.cpu6.l1c.WriteReq_avg_miss_latency::total 43893.173019                       # average WriteReq miss latency
system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740                       # average overall miss latency
system.cpu6.l1c.demand_avg_miss_latency::total 38432.141740                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740                       # average overall miss latency
system.cpu6.l1c.overall_avg_miss_latency::total 38432.141740                       # average overall miss latency
system.cpu6.l1c.blocked_cycles::no_mshrs    253794713                       # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs               68612                       # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3698.984332                       # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu6.l1c.writebacks::writebacks          11849                       # number of writebacks
system.cpu6.l1c.writebacks::total               11849                       # number of writebacks
system.cpu6.l1c.ReadReq_mshr_misses::cpu6        37109                       # number of ReadReq MSHR misses
system.cpu6.l1c.ReadReq_mshr_misses::total        37109                       # number of ReadReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23142                       # number of WriteReq MSHR misses
system.cpu6.l1c.WriteReq_mshr_misses::total        23142                       # number of WriteReq MSHR misses
system.cpu6.l1c.demand_mshr_misses::cpu6        60251                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.demand_mshr_misses::total        60251                       # number of demand (read+write) MSHR misses
system.cpu6.l1c.overall_mshr_misses::cpu6        60251                       # number of overall MSHR misses
system.cpu6.l1c.overall_mshr_misses::total        60251                       # number of overall MSHR misses
system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   1262548698                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_miss_latency::total   1262548698                       # number of ReadReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    992541214                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.WriteReq_mshr_miss_latency::total    992541214                       # number of WriteReq MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::cpu6   2255089912                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.demand_mshr_miss_latency::total   2255089912                       # number of demand (read+write) MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::cpu6   2255089912                       # number of overall MSHR miss cycles
system.cpu6.l1c.overall_mshr_miss_latency::total   2255089912                       # number of overall MSHR miss cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    877981455                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    877981455                       # number of ReadReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    574689009                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    574689009                       # number of WriteReq MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1452670464                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1452670464                       # number of overall MSHR uncacheable cycles
system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.831071                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.ReadReq_mshr_miss_rate::total     0.831071                       # mshr miss rate for ReadReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953877                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.WriteReq_mshr_miss_rate::total     0.953877                       # mshr miss rate for WriteReq accesses
system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.874305                       # mshr miss rate for demand accesses
system.cpu6.l1c.demand_mshr_miss_rate::total     0.874305                       # mshr miss rate for demand accesses
system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.874305                       # mshr miss rate for overall accesses
system.cpu6.l1c.overall_mshr_miss_rate::total     0.874305                       # mshr miss rate for overall accesses
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723                       # average ReadReq mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 34022.708723                       # average ReadReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809                       # average WriteReq mshr miss latency
system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 42889.171809                       # average WriteReq mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992                       # average overall mshr miss latency
system.cpu6.l1c.demand_avg_mshr_miss_latency::total 37428.256992                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992                       # average overall mshr miss latency
system.cpu6.l1c.overall_avg_mshr_miss_latency::total 37428.256992                       # average overall mshr miss latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
system.cpu7.num_reads                           99694                       # number of read accesses completed
system.cpu7.num_writes                          53501                       # number of write accesses completed
system.cpu7.num_copies                              0                       # number of copy accesses completed
system.cpu7.l1c.replacements                    27727                       # number of replacements
system.cpu7.l1c.tagsinuse                  346.094259                       # Cycle average of tags in use
system.cpu7.l1c.total_refs                      11534                       # Total number of references to valid blocks.
system.cpu7.l1c.sampled_refs                    28062                       # Sample count of references to valid blocks.
system.cpu7.l1c.avg_refs                     0.411018                       # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.cpu7.l1c.occ_blocks::cpu7           346.094259                       # Average occupied blocks per requestor
system.cpu7.l1c.occ_percent::cpu7            0.675965                       # Average percentage of cache occupancy
system.cpu7.l1c.occ_percent::total           0.675965                       # Average percentage of cache occupancy
system.cpu7.l1c.ReadReq_hits::cpu7               7593                       # number of ReadReq hits
system.cpu7.l1c.ReadReq_hits::total              7593                       # number of ReadReq hits
system.cpu7.l1c.WriteReq_hits::cpu7              1111                       # number of WriteReq hits
system.cpu7.l1c.WriteReq_hits::total             1111                       # number of WriteReq hits
system.cpu7.l1c.demand_hits::cpu7                8704                       # number of demand (read+write) hits
system.cpu7.l1c.demand_hits::total               8704                       # number of demand (read+write) hits
system.cpu7.l1c.overall_hits::cpu7               8704                       # number of overall hits
system.cpu7.l1c.overall_hits::total              8704                       # number of overall hits
system.cpu7.l1c.ReadReq_misses::cpu7            37155                       # number of ReadReq misses
system.cpu7.l1c.ReadReq_misses::total           37155                       # number of ReadReq misses
system.cpu7.l1c.WriteReq_misses::cpu7           23121                       # number of WriteReq misses
system.cpu7.l1c.WriteReq_misses::total          23121                       # number of WriteReq misses
system.cpu7.l1c.demand_misses::cpu7             60276                       # number of demand (read+write) misses
system.cpu7.l1c.demand_misses::total            60276                       # number of demand (read+write) misses
system.cpu7.l1c.overall_misses::cpu7            60276                       # number of overall misses
system.cpu7.l1c.overall_misses::total           60276                       # number of overall misses
system.cpu7.l1c.ReadReq_miss_latency::cpu7   1287127315                       # number of ReadReq miss cycles
system.cpu7.l1c.ReadReq_miss_latency::total   1287127315                       # number of ReadReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::cpu7   1006139538                       # number of WriteReq miss cycles
system.cpu7.l1c.WriteReq_miss_latency::total   1006139538                       # number of WriteReq miss cycles
system.cpu7.l1c.demand_miss_latency::cpu7   2293266853                       # number of demand (read+write) miss cycles
system.cpu7.l1c.demand_miss_latency::total   2293266853                       # number of demand (read+write) miss cycles
system.cpu7.l1c.overall_miss_latency::cpu7   2293266853                       # number of overall miss cycles
system.cpu7.l1c.overall_miss_latency::total   2293266853                       # number of overall miss cycles
system.cpu7.l1c.ReadReq_accesses::cpu7          44748                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.ReadReq_accesses::total         44748                       # number of ReadReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::cpu7         24232                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.WriteReq_accesses::total        24232                       # number of WriteReq accesses(hits+misses)
system.cpu7.l1c.demand_accesses::cpu7           68980                       # number of demand (read+write) accesses
system.cpu7.l1c.demand_accesses::total          68980                       # number of demand (read+write) accesses
system.cpu7.l1c.overall_accesses::cpu7          68980                       # number of overall (read+write) accesses
system.cpu7.l1c.overall_accesses::total         68980                       # number of overall (read+write) accesses
system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.830316                       # miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_miss_rate::total     0.830316                       # miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954152                       # miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_miss_rate::total     0.954152                       # miss rate for WriteReq accesses
system.cpu7.l1c.demand_miss_rate::cpu7       0.873818                       # miss rate for demand accesses
system.cpu7.l1c.demand_miss_rate::total      0.873818                       # miss rate for demand accesses
system.cpu7.l1c.overall_miss_rate::cpu7      0.873818                       # miss rate for overall accesses
system.cpu7.l1c.overall_miss_rate::total     0.873818                       # miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409                       # average ReadReq miss latency
system.cpu7.l1c.ReadReq_avg_miss_latency::total 34642.102409                       # average ReadReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916                       # average WriteReq miss latency
system.cpu7.l1c.WriteReq_avg_miss_latency::total 43516.263916                       # average WriteReq miss latency
system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147                       # average overall miss latency
system.cpu7.l1c.demand_avg_miss_latency::total 38046.102147                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147                       # average overall miss latency
system.cpu7.l1c.overall_avg_miss_latency::total 38046.102147                       # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs    254008986                       # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs               69036                       # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3679.369981                       # average number of cycles each access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
system.cpu7.l1c.writebacks::writebacks          11797                       # number of writebacks
system.cpu7.l1c.writebacks::total               11797                       # number of writebacks
system.cpu7.l1c.ReadReq_mshr_misses::cpu7        37155                       # number of ReadReq MSHR misses
system.cpu7.l1c.ReadReq_mshr_misses::total        37155                       # number of ReadReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23121                       # number of WriteReq MSHR misses
system.cpu7.l1c.WriteReq_mshr_misses::total        23121                       # number of WriteReq MSHR misses
system.cpu7.l1c.demand_mshr_misses::cpu7        60276                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.demand_mshr_misses::total        60276                       # number of demand (read+write) MSHR misses
system.cpu7.l1c.overall_mshr_misses::cpu7        60276                       # number of overall MSHR misses
system.cpu7.l1c.overall_mshr_misses::total        60276                       # number of overall MSHR misses
system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   1249829653                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_miss_latency::total   1249829653                       # number of ReadReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    982928032                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.WriteReq_mshr_miss_latency::total    982928032                       # number of WriteReq MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::cpu7   2232757685                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.demand_mshr_miss_latency::total   2232757685                       # number of demand (read+write) MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::cpu7   2232757685                       # number of overall MSHR miss cycles
system.cpu7.l1c.overall_mshr_miss_latency::total   2232757685                       # number of overall MSHR miss cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    901961636                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    901961636                       # number of ReadReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    558194703                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    558194703                       # number of WriteReq MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1460156339                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1460156339                       # number of overall MSHR uncacheable cycles
system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.830316                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.ReadReq_mshr_miss_rate::total     0.830316                       # mshr miss rate for ReadReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954152                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.WriteReq_mshr_miss_rate::total     0.954152                       # mshr miss rate for WriteReq accesses
system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.873818                       # mshr miss rate for demand accesses
system.cpu7.l1c.demand_mshr_miss_rate::total     0.873818                       # mshr miss rate for demand accesses
system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.873818                       # mshr miss rate for overall accesses
system.cpu7.l1c.overall_mshr_miss_rate::total     0.873818                       # mshr miss rate for overall accesses
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764                       # average ReadReq mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 33638.262764                       # average ReadReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466                       # average WriteReq mshr miss latency
system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 42512.349466                       # average WriteReq mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808                       # average overall mshr miss latency
system.cpu7.l1c.demand_avg_mshr_miss_latency::total 37042.233808                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808                       # average overall mshr miss latency
system.cpu7.l1c.overall_avg_mshr_miss_latency::total 37042.233808                       # average overall mshr miss latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
