
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.431420                       # Number of seconds simulated
sim_ticks                                2431419954000                       # Number of ticks simulated
final_tick                               2431419954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1031283                       # Simulator instruction rate (inst/s)
host_op_rate                                  1150922                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1629547552                       # Simulator tick rate (ticks/s)
host_mem_usage                                 230584                       # Number of bytes of host memory used
host_seconds                                  1492.08                       # Real time elapsed on the host
sim_insts                                  1538759609                       # Number of instructions simulated
sim_ops                                    1717270343                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst             39424                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data         172726592                       # Number of bytes read from this memory
system.physmem.bytes_read::total            172766016                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst        39424                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total           39424                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     75006720                       # Number of bytes written to this memory
system.physmem.bytes_written::total          75006720                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst                616                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            2698853                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               2699469                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1171980                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1171980                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                16214                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             71039391                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                71055605                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           16214                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              16214                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          30848937                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               30848937                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          30848937                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               16214                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            71039391                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total              101904542                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                   46                       # Number of system calls
system.cpu.numCycles                       4862839908                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                  1538759609                       # Number of instructions committed
system.cpu.committedOps                    1717270343                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    177498328                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   1536941850                       # number of integer instructions
system.cpu.num_fp_insts                            36                       # number of float instructions
system.cpu.num_int_register_reads          9304894713                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1675132418                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   24                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                  16                       # number of times the floating registers were written
system.cpu.num_mem_refs                     660773816                       # number of memory refs
system.cpu.num_load_insts                   485926770                       # Number of load instructions
system.cpu.num_store_insts                  174847046                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 4862839908                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                      7                       # number of replacements
system.cpu.icache.tagsinuse                514.872896                       # Cycle average of tags in use
system.cpu.icache.total_refs               1544564961                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               2420948.214734                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     514.872896                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.251403                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.251403                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   1544564961                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      1544564961                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    1544564961                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       1544564961                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   1544564961                       # number of overall hits
system.cpu.icache.overall_hits::total      1544564961                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst          638                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total           638                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst          638                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total            638                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst          638                       # number of overall misses
system.cpu.icache.overall_misses::total           638                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst     34804000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total     34804000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst     34804000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total     34804000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst     34804000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total     34804000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   1544565599                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   1544565599                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   1544565599                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   1544565599                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   1544565599                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   1544565599                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000000                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000000                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 54551.724138                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 54551.724138                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 54551.724138                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total          638                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst          638                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32890000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total     32890000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32890000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total     32890000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32890000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total     32890000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000000                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000000                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000000                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51551.724138                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 51551.724138                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51551.724138                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                9111140                       # number of replacements
system.cpu.dcache.tagsinuse               4083.719979                       # Cycle average of tags in use
system.cpu.dcache.total_refs                645855060                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle            25923025000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4083.719979                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.997002                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.997002                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    475158040                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       475158040                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      170696898                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     645854938                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        645854938                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    645854938                       # number of overall hits
system.cpu.dcache.overall_hits::total       645854938                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      7226087                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       7226087                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      1889149                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      1889149                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      9115236                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        9115236                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 177140908000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  63824222000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  63824222000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 240965130000                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 240965130000                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 240965130000                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 240965130000                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    482384127                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    482384127                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    654970174                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    654970174                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    654970174                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    654970174                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.014980                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.014980                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010946                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.010946                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.013917                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.013917                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.013917                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.013917                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24514.084594                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 33784.641656                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 26435.424162                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 26435.424162                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      3061985                       # number of writebacks
system.cpu.dcache.writebacks::total           3061985                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226087                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      7226087                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889149                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1889149                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      9115236                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      9115236                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  58156775000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  58156775000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 213619422000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 213619422000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.014980                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.014980                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.010946                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.013917                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.013917                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.013917                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.013917                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21514.084594                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30784.641656                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23435.424162                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23435.424162                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements               2687066                       # number of replacements
system.cpu.l2cache.tagsinuse             26134.517233                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 7569171                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs               2714383                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  2.788542                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          538044123000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 11106.896016                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     11.181020                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data  15016.440197                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.338956                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.000341                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.458265                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.797562                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst           22                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      5417142                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        5417164                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      3061985                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      3061985                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       999241                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       999241                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst           22                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      6416383                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         6416405                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst           22                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      6416383                       # number of overall hits
system.cpu.l2cache.overall_hits::total        6416405                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst          616                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data      1808945                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total      1809561                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       889908                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       889908                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst          616                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data      2698853                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total       2699469                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst          616                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data      2698853                       # number of overall misses
system.cpu.l2cache.overall_misses::total      2699469                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32032000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  94065140000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  94097172000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46275216000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  46275216000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst     32032000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 140372388000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst     32032000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 140372388000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst          638                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      7226087                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      7226725                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      3061985                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      3061985                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889149                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1889149                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst          638                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      9115236                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      9115874                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst          638                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      9115236                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      9115874                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.965517                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250335                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.250398                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.471063                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.471063                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965517                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.296082                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.296128                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965517                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.296082                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.296128                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total        52000                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total        52000                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks      1171980                       # number of writebacks
system.cpu.l2cache.writebacks::total          1171980                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          616                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1808945                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total      1809561                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       889908                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       889908                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst          616                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data      2698853                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total      2699469                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst          616                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data      2698853                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total      2699469                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24640000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  72357800000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  72382440000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  35596320000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  35596320000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24640000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24640000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250335                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.250398                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.471063                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.471063                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.296082                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.296128                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.296082                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.296128                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
