
---------- Begin Simulation Statistics ----------
sim_seconds                                  1.658730                       # Number of seconds simulated
sim_ticks                                1658729604000                       # Number of ticks simulated
final_tick                               1658729604000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 615589                       # Simulator instruction rate (inst/s)
host_op_rate                                  1138293                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             1234881669                       # Simulator tick rate (ticks/s)
host_mem_usage                                 229524                       # Number of bytes of host memory used
host_seconds                                  1343.23                       # Real time elapsed on the host
sim_insts                                   826877145                       # Number of instructions simulated
sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst            148544                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          36946432                       # Number of bytes read from this memory
system.physmem.bytes_read::total             37094976                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       148544                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          148544                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     26349376                       # Number of bytes written to this memory
system.physmem.bytes_written::total          26349376                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2321                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             577288                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                579609                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          411709                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               411709                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst                89553                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             22273933                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                22363486                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           89553                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              89553                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks          15885275                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total               15885275                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks          15885275                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               89553                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            22273933                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               38248761                       # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls                  551                       # Number of system calls
system.cpu.numCycles                       3317459208                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   826877145                       # Number of instructions committed
system.cpu.committedOps                    1528988757                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
system.cpu.num_func_calls                           0                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
system.cpu.num_int_insts                   1528317615                       # number of integer instructions
system.cpu.num_fp_insts                             0                       # number of float instructions
system.cpu.num_int_register_reads          4441632810                       # number of times the integer registers were read
system.cpu.num_int_register_writes         1993077484                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_mem_refs                     533262345                       # number of memory refs
system.cpu.num_load_insts                   384102160                       # Number of load instructions
system.cpu.num_store_insts                  149160185                       # Number of store instructions
system.cpu.num_idle_cycles                          0                       # Number of idle cycles
system.cpu.num_busy_cycles                 3317459208                       # Number of busy cycles
system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
system.cpu.idle_fraction                            0                       # Percentage of idle cycles
system.cpu.icache.replacements                   1253                       # number of replacements
system.cpu.icache.tagsinuse                882.231489                       # Cycle average of tags in use
system.cpu.icache.total_refs               1068344296                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs               379653.267946                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     882.231489                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.430777                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.430777                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst   1068344296                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total      1068344296                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst    1068344296                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total       1068344296                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst   1068344296                       # number of overall hits
system.cpu.icache.overall_hits::total      1068344296                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst         2814                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total          2814                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst         2814                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total           2814                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst         2814                       # number of overall misses
system.cpu.icache.overall_misses::total          2814                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    136878000                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    136878000                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    136878000                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    136878000                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    136878000                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    136878000                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst   1068347110                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total   1068347110                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst   1068347110                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total   1068347110                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst   1068347110                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total   1068347110                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000003                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000003                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000003                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 48641.791045                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 48641.791045                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 48641.791045                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total         2814                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst         2814                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total         2814                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst         2814                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total         2814                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    128436000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    128436000                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    128436000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    128436000                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    128436000                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    128436000                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000003                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000003                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000003                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 45641.791045                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 45641.791045                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 45641.791045                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                2514362                       # number of replacements
system.cpu.dcache.tagsinuse               4086.472055                       # Cycle average of tags in use
system.cpu.dcache.total_refs                530743932                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                 210.741625                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle             8216675000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data    4086.472055                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.997674                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.997674                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data    382374775                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       382374775                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    148369157                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      148369157                       # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data     530743932                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        530743932                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    530743932                       # number of overall hits
system.cpu.dcache.overall_hits::total       530743932                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      1727414                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       1727414                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       791044                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       791044                       # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data      2518458                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        2518458                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      2518458                       # number of overall misses
system.cpu.dcache.overall_misses::total       2518458                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  38012508000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  38012508000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  21492013500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  21492013500                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  59504521500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  59504521500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  59504521500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  59504521500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    384102189                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    384102189                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    533262390                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    533262390                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    533262390                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    533262390                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004497                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.004497                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005303                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.005303                       # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.004723                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.004723                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.004723                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.004723                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 22005.441660                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 27169.175798                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 23627.363053                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 23627.363053                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      2223170                       # number of writebacks
system.cpu.dcache.writebacks::total           2223170                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1727414                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      1727414                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data       791044                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total       791044                       # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      2518458                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      2518458                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      2518458                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      2518458                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32830264000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  32830264000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19118876000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  19118876000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  51949140000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  51949140000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  51949140000                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  51949140000                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004497                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.004497                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005303                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.005303                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.004723                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.004723                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19005.440502                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24169.168845                       # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 20627.360075                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 20627.360075                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.replacements                568906                       # number of replacements
system.cpu.l2cache.tagsinuse             21228.193311                       # Cycle average of tags in use
system.cpu.l2cache.total_refs                 3146531                       # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs                587958                       # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs                  5.351625                       # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle          896565143000                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 13679.064710                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst     30.006309                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data   7519.122292                       # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks     0.417452                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst     0.000916                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data     0.229465                       # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total        0.647833                       # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst          493                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1398159                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1398652                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      2223170                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      2223170                       # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       543011                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       543011                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst          493                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1941170                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         1941663                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst          493                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1941170                       # number of overall hits
system.cpu.l2cache.overall_hits::total        1941663                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst         2321                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data       329255                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total       331576                       # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       248033                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       248033                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2321                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       577288                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        579609                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2321                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       577288                       # number of overall misses
system.cpu.l2cache.overall_misses::total       579609                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    120692000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17121260000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total  17241952000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12897722000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  12897722000                       # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    120692000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  30018982000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  30139674000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    120692000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  30018982000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  30139674000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst         2814                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1727414                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1730228                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      2223170                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      2223170                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       791044                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       791044                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst         2814                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      2518458                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2521272                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst         2814                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      2518458                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2521272                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.824805                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.190606                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.191637                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.313551                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.313551                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.824805                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.229223                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.229888                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.824805                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.229223                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.229888                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total        52000                       # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.024190                       # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 52000.010352                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 52000.010352                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       411709                       # number of writebacks
system.cpu.l2cache.writebacks::total           411709                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2321                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       329255                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total       331576                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       248033                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       248033                       # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2321                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       577288                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       579609                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2321                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       577288                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       579609                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     92840000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  13170200000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13263040000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9921320000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9921320000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     92840000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23091520000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  23184360000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     92840000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23091520000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  23184360000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.190606                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.191637                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.313551                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.313551                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229223                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.229888                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229223                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.229888                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total        40000                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total        40000                       # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total        40000                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
