
---------- Begin Simulation Statistics ----------
sim_seconds                                  2.332330                       # Number of seconds simulated
sim_ticks                                2332330037000                       # Number of ticks simulated
final_tick                               2332330037000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1412842                       # Simulator instruction rate (inst/s)
host_op_rate                                  1823742                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            55482154888                       # Simulator tick rate (ticks/s)
host_mem_usage                                 382804                       # Number of bytes of host memory used
host_seconds                                    42.04                       # Real time elapsed on the host
sim_insts                                    59392246                       # Number of instructions simulated
sim_ops                                      76665494                       # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker         1536                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            941920                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10043536                       # Number of bytes read from this memory
system.physmem.bytes_read::total            122661296                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       941920                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          941920                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      6574400                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data        3015816                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9590216                       # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd      13959168                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker           24                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker           15                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              20920                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             156964                       # Number of read requests responded to by this memory
system.physmem.num_reads::total              14137091                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          102725                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data            753954                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               856679                       # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd        47880592                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker            659                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker            412                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               403854                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              4306224                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                52591740                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          403854                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             403854                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           2818812                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data             1293049                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                4111861                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           2818812                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd       47880592                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker           659                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker           412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              403854                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             5599273                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               56703601                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total              5                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             9                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                9                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            9                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            9                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            9                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               9                       # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements                        117012                       # number of replacements
system.l2c.tagsinuse                     24288.656748                       # Cycle average of tags in use
system.l2c.total_refs                         1527554                       # Total number of references to valid blocks.
system.l2c.sampled_refs                        146810                       # Sample count of references to valid blocks.
system.l2c.avg_refs                         10.404972                       # Average number of references to valid blocks.
system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
system.l2c.occ_blocks::writebacks        13693.996987                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.dtb.walker        7.872000                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.itb.walker        1.975558                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.inst           5248.163956                       # Average occupied blocks per requestor
system.l2c.occ_blocks::cpu.data           5336.648246                       # Average occupied blocks per requestor
system.l2c.occ_percent::writebacks           0.208954                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.dtb.walker       0.000120                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker       0.000030                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.inst             0.080081                       # Average percentage of cache occupancy
system.l2c.occ_percent::cpu.data             0.081431                       # Average percentage of cache occupancy
system.l2c.occ_percent::total                0.370615                       # Average percentage of cache occupancy
system.l2c.ReadReq_hits::cpu.dtb.walker          7515                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.itb.walker          3139                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.inst              835264                       # number of ReadReq hits
system.l2c.ReadReq_hits::cpu.data              357385                       # number of ReadReq hits
system.l2c.ReadReq_hits::total                1203303                       # number of ReadReq hits
system.l2c.Writeback_hits::writebacks          605735                       # number of Writeback hits
system.l2c.Writeback_hits::total               605735                       # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
system.l2c.ReadExReq_hits::cpu.data            106156                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               106156                       # number of ReadExReq hits
system.l2c.demand_hits::cpu.dtb.walker           7515                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.itb.walker           3139                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.inst               835264                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu.data               463541                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 1309459                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu.dtb.walker          7515                       # number of overall hits
system.l2c.overall_hits::cpu.itb.walker          3139                       # number of overall hits
system.l2c.overall_hits::cpu.inst              835264                       # number of overall hits
system.l2c.overall_hits::cpu.data              463541                       # number of overall hits
system.l2c.overall_hits::total                1309459                       # number of overall hits
system.l2c.ReadReq_misses::cpu.dtb.walker           24                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.itb.walker           15                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.inst             14304                       # number of ReadReq misses
system.l2c.ReadReq_misses::cpu.data             17465                       # number of ReadReq misses
system.l2c.ReadReq_misses::total                31808                       # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu.data           2918                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total              2918                       # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu.data          141050                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             141050                       # number of ReadExReq misses
system.l2c.demand_misses::cpu.dtb.walker           24                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.itb.walker           15                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.inst              14304                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu.data             158515                       # number of demand (read+write) misses
system.l2c.demand_misses::total                172858                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu.dtb.walker           24                       # number of overall misses
system.l2c.overall_misses::cpu.itb.walker           15                       # number of overall misses
system.l2c.overall_misses::cpu.inst             14304                       # number of overall misses
system.l2c.overall_misses::cpu.data            158515                       # number of overall misses
system.l2c.overall_misses::total               172858                       # number of overall misses
system.l2c.ReadReq_accesses::cpu.dtb.walker         7539                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.itb.walker         3154                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.inst          849568                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu.data          374850                       # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total            1235111                       # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks       605735                       # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total           605735                       # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu.data         2944                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total            2944                       # number of UpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu.data        247206                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           247206                       # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu.dtb.walker         7539                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.itb.walker         3154                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.inst           849568                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu.data           622056                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             1482317                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu.dtb.walker         7539                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.itb.walker         3154                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.inst          849568                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu.data          622056                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            1482317                       # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.003183                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.004756                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.inst       0.016837                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu.data       0.046592                       # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total          0.025753                       # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu.data     0.991168                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.991168                       # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu.data     0.570577                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.570577                       # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu.dtb.walker     0.003183                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.itb.walker     0.004756                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.inst        0.016837                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu.data        0.254824                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.116613                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu.dtb.walker     0.003183                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.itb.walker     0.004756                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.inst       0.016837                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu.data       0.254824                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.116613                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.fast_writes                              0                       # number of fast writes performed
system.l2c.cache_copies                             0                       # number of cache copies performed
system.l2c.writebacks::writebacks              102725                       # number of writebacks
system.l2c.writebacks::total                   102725                       # number of writebacks
system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                     14971229                       # DTB read hits
system.cpu.dtb.read_misses                       7293                       # DTB read misses
system.cpu.dtb.write_hits                    11217018                       # DTB write hits
system.cpu.dtb.write_misses                      2181                       # DTB write misses
system.cpu.dtb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                     3492                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                    174                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                       452                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                 14978522                       # DTB read accesses
system.cpu.dtb.write_accesses                11219199                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                          26188247                       # DTB hits
system.cpu.dtb.misses                            9474                       # DTB misses
system.cpu.dtb.accesses                      26197721                       # DTB accesses
system.cpu.itb.inst_hits                     60403303                       # ITB inst hits
system.cpu.itb.inst_misses                       4471                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            2                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                1439                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                      63                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                     2343                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                 60407774                       # ITB inst accesses
system.cpu.itb.hits                          60403303                       # DTB hits
system.cpu.itb.misses                            4471                       # DTB misses
system.cpu.itb.accesses                      60407774                       # DTB accesses
system.cpu.numCycles                       4664583062                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                    59392246                       # Number of instructions committed
system.cpu.committedOps                      76665494                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses              68281415                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
system.cpu.num_func_calls                     1972385                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts      7647793                       # number of instructions that are conditional controls
system.cpu.num_int_insts                     68281415                       # number of integer instructions
system.cpu.num_fp_insts                         10269                       # number of float instructions
system.cpu.num_int_register_reads           345981857                       # number of times the integer registers were read
system.cpu.num_int_register_writes           73062916                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                 7493                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                2780                       # number of times the floating registers were written
system.cpu.num_mem_refs                      27361692                       # number of memory refs
system.cpu.num_load_insts                    15639569                       # Number of load instructions
system.cpu.num_store_insts                   11722123                       # Number of store instructions
system.cpu.num_idle_cycles               4586814358.980880                       # Number of idle cycles
system.cpu.num_busy_cycles               77768703.019120                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.016672                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.983328                       # Percentage of idle cycles
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    82795                       # number of quiesce instructions executed
system.cpu.icache.replacements                 850612                       # number of replacements
system.cpu.icache.tagsinuse                511.678549                       # Cycle average of tags in use
system.cpu.icache.total_refs                 59554939                       # Total number of references to valid blocks.
system.cpu.icache.sampled_refs                 851124                       # Sample count of references to valid blocks.
system.cpu.icache.avg_refs                  69.972106                       # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle             5708999000                       # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst     511.678549                       # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst      0.999372                       # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total         0.999372                       # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst     59554939                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        59554939                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      59554939                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         59554939                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     59554939                       # number of overall hits
system.cpu.icache.overall_hits::total        59554939                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       851124                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        851124                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       851124                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         851124                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       851124                       # number of overall misses
system.cpu.icache.overall_misses::total        851124                       # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst     60406063                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     60406063                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     60406063                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     60406063                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     60406063                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     60406063                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014090                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.014090                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.014090                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.014090                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.014090                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.014090                       # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        44595                       # number of writebacks
system.cpu.icache.writebacks::total             44595                       # number of writebacks
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dcache.replacements                 623347                       # number of replacements
system.cpu.dcache.tagsinuse                511.997030                       # Cycle average of tags in use
system.cpu.dcache.total_refs                 23628362                       # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs                 623859                       # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs                  37.874523                       # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle               21763000                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data     511.997030                       # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data     13180074                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        13180074                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      9962087                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        9962087                       # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data       236035                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total       236035                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data       247222                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total       247222                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      23142161                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         23142161                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     23142161                       # number of overall hits
system.cpu.dcache.overall_hits::total        23142161                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       365465                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        365465                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       250150                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       250150                       # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data        11188                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total        11188                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       615615                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         615615                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       615615                       # number of overall misses
system.cpu.dcache.overall_misses::total        615615                       # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data     13545539                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     13545539                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     10212237                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     10212237                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247223                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total       247223                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data       247222                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total       247222                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     23757776                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     23757776                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     23757776                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     23757776                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026980                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.026980                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024495                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.024495                       # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045255                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.045255                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.025912                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.025912                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.025912                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.025912                       # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks       561140                       # number of writebacks
system.cpu.dcache.writebacks::total            561140                       # number of writebacks
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.iocache.replacements                         0                       # number of replacements
system.iocache.tagsinuse                            0                       # Cycle average of tags in use
system.iocache.total_refs                           0                       # Total number of references to valid blocks.
system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
system.iocache.avg_refs                           nan                       # Average number of references to valid blocks.
system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate

---------- End Simulation Statistics   ----------
